WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 270

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1.5.4
Table 74.
9.1.5.5
Table 75.
270
Table Offset, Offset 0xA4 (R/W)
MSI-X Table Offset
PBA Offset, Offset 0xA8 (R/W)
MSI-X PBA Offset
To request service using a given MSI-X table entry, a function performs a Dword
memory write transaction using the contents of the Message Data field entry for data,
the contents of the Message Upper Address field for the upper 32 bits of address, and
the contents of the Message Address field entry for the lower 32 bits of address. A
memory read transaction from the address targeted by the MSI-X message produces
undefined results.
indicated by the Table Size field in the MSI-X Message Control register. For a given
arbitrary MSI-X Table entry K, its starting address can be calculated with the formula:
For the associated pending bit K, its address for Qword access and bit number within
that Qword can be calculated with the formulas:
Software that chooses to read pending bit K with Dword accesses can use these
formulas:
Table Offset
Table BIR
PBA Offset
PBA BIR
MSI-X table entries and pending bits are each numbered 0 through N-1, where N-1 is
Field
Field
31:3
2:0
Entry starting address = Table base + K*16
QWORD address = PBA base + (K div 64)*8
QWORD bit# = K mod 64
DWORD address = PBA base + (K div 32)*4
DWORD bit# = K mod 32
Bits
31:3
2:0
Bits
0x400
0x3
Default
0x000
0x3
Default
RO
RO
RO
RO
Type
Type
Used as an offset from the address contained by one of
the function’s BARs to point to the base of the MSI-X
PBA. The lower three PBA BIR bits are masked off (set to
zero) by software to form a 32-bit Qword-aligned offset.
Indicates which one of a function’s BARs, located
beginning at 0x10 in configuration space, is used to map
the function’s MSI-X PBA into memory space.
A BIR value of three indicates that the PBA is mapped in
BAR 3.
Used as an offset from the address contained by one of
the function’s Base Address registers to point to the
base of the MSI-X table. The lower three table BIR bits
are masked off (set to zero) by software to form a 32-bit
Qword-aligned offset.
Indicates which one of a function’s BARs, located
beginning at 0x10 in configuration space, is used to map
the function’s MSI-X table into memory space.
A BIR value of three indicates that the table is mapped
in BAR 3.
82574 GbE Controller—Programing Interface
Description
Description