WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 311

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.2.24
Note:
10.2.2.25
EEPROM Write Register - EEWR (0x0102C; RW)
EEWR has direct access regardless of a valid signature in the NVM.
SW FLASH Burst Control Register - FLSWCTL (0x1030; RW)
START
DONE
ADDR
DATA
ADDR
CMD
CMDV
FLBUSY
Reserved
FLUDONE
DONE
WRDONE
Field
Field
0
1
15:2
31:16
23:0
25:24
26
27
28
29
30
31
Bit(s)
Bit(s)
0b
1b
0x0
0x0
0x0
00b
0b
0b
0b
0b
1b
1b
Default
Default
Start Write
Writing a 1b to this bit causes the 82574 to write a 16-bit word at the
address stored in the ADDR field in the external NVM. The data is
fetched from the DATA field. This bit is self-clearing.
Write Done
Set to 1b when the write completes. Set to 0b when the write is in
progress. Writes by software are ignored.
Write Address
This field is written by software along with Start Write to indicate the
word address of the word to read.
Write Data
Data written to the NVM.
Address
This field is written by software along with Start Read or Start write to
indicate the Flash address to read or write.
Command
Indicates which command should be executed. Valid only when the
CMDV bit is set.
00b = Reserved.
01b = DMA Write command (write up to 256 bytes).
10b = Reserved.
11b = Reserved.
Command Valid
When set, indicates that software issues a new command.
Cleared by hardware at the end of the command.
Flash Busy
This bit indicates that the Flash is busy processing a Flash transaction
and should not be accessed.
Reserved
Flash Update Done
This bit is set by the 82574 when it completes updating the Flash.
Software should clear it to zero before it updates the Flash.
Write Done
This bit clears after CMDV is set by software and is set back again
when the Flash write transaction is done.
When writing a burst transaction the bit is cleared every time
software writes FLSWDATA.
Global Done
This bit clears after the CMDV bit is set by software and is set back
again when the all Flash read/write transactions complete. For
example, the Flash unit finished to read/write all the requested read/
writes.
Description
Description
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