WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 418

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.0
11.1
11.2
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Diagnostics
To assist in test and debug of the software device driver, a set of software-usable
features have been provided in the component. These features include controls for
specific test-mode usage, as well as some registers for verifying the 82574’s internal
state against what the software device driver is expecting.
Introduction
The 82574L provides software visibility (and controllability) into certain major internal
data structures, including all of the transmit and receive FIFO space. However,
interlocks are not provided for any operations, so diagnostic accesses can only be
performed under very controlled circumstances.
The 82574L also provides software-controllable support for certain loopback modes, to
enable a software device driver to test transmit and receive flows to itself. Loopback
modes can also be used to diagnose communication problems and attempt to isolate
the location of a break in the communications path.
FIFO Pointer Accessibility
The 82574L’s internal pointers into its transmit and receive data FIFOs are visible
through the head and tail diagnostic data FIFO registers. See
Diagnostics software can read these FIFO pointers to confirm an expected hardware
state following a sequence of operation(s). Diagnostic software can further write to
these pointers as a partial-step to verify expected FIFO contents following a specific
operation, or to subsequently write data directly to the data FIFOs.
FIFO Data Accessibility
The 82574L’s internal transmit and receive data FIFOs contents are directly readable
and writeable through the PBM register. The specific locations read or written are
determined by the values of the FIFO pointers, which can be read and written. When
accessing the actual FIFO data structures, locations must be accessed as 32-bit words.
See
section
10.2.12.
82574 GbE Controller—Diagnostics
section
10.2.12.