WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 260

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 58.
9.1.2.1
9.1.2.2
9.1.2.3
260
PCI-Compatible Configuration Registers
Explanation of the various registers in the 82574 is as follows.
Vendor ID (Offset 0x0)
This is a read-only register that has the same value for all PCI functions. It uniquely
identifies Intel products. The field default value is 0x8086.
Device ID (Offset 0x2)
This is a read-only register. The value is loaded from NVM. Default value is 0x10D3 for
the 82574.
Command Reg (Offset 0x4)
Read-write register. Layout is as follows. Shaded bits are not used by this
implementation and are hardwired to 0b.
0x28
0x2C
0x30
0x34
0x38
0x3C
LAN
Byte Offset
Bit(s)
Function
15:11
10
0
1
2
3
4
5
6
7
8
9
PCI
Init Value
0x10D3
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Max_Latency (0x00)
Default
Value
Byte 3
I/O Access Enable.
Memory Access Enable.
Enable Mastering LAN R/W field.
Special Cycle Monitoring – Hardwired to 0b.
MWI Enable – Hardwired to 0b.
Palette Snoop Enable – Hardwired to 0b.
Parity Error Response.
Wait Cycle Enable – Hardwired to 0b.
SERR# Enable.
Fast Back-to-Back Enable – Hardwired to 0b.
Interrupt Disable
Controls the ability of a PCIe device to generate a legacy interrupt
message. When set, the device can’t generate legacy interrupt
messages
Reserved
Subsystem ID (0x0000)
0Dh
NVM Address
.
Reserved (0x000000)
Cardbus CIS Pointer (0x00000000)
Min_Grant
10/100/1000mbit Ethernet controller, x1 PCIe,
copper
Byte 2
(0x00)
Expansion ROM Base Address
Reserved (0x00000000)
Description
82574 GbE Controller—Programing Interface
Meaning
Interrupt Pin
Subsystem Vendor ID (0x8086)
Byte 1
(0x01)
Cap_Ptr (0xC8)
Interrupt Line
Byte 0
(0x00)