WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 451

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Design Considerations—82574 GbE Controller
13.5.5.8
13.5.5.9
13.5.5.10
13.5.5.11
Routing 1.9 V dc to the Magnetics Center Tap
The central-tap 1.9 V dc should be delivered as a solid supply plane (1.9 V dc) directly
to the magnetic module or, if this is not possible, by a short and thick trace (lower than
0.2 DC resistance). The decoupling capacitors for the central tap pins should be
placed as close as possible to the magnetic component. This improves both EMI and
IEEE compliance.
Impedance Discontinuities
Impedance discontinuities cause unwanted signal reflections. Minimize vias (signal
through holes) and other transmission line irregularities. If vias must be used, a
reasonable budget is two per differential trace. Unused pads and stub traces should
also be avoided.
Reducing Circuit Inductance
Traces should be routed over a continuous reference plane with no interruptions. If
there are vacant areas on a reference or power plane, the signal conductors should not
cross the vacant area. This causes impedance mismatches and associated radiated
noise levels. Noisy logic grounds should be separated from analog signal grounds to
reduce coupling. Noisy logic grounds can sometimes affect sensitive DC subsystems
such as analog to digital conversion, operational amplifiers, etc. All ground vias should
be connected to every ground plane; and similarly, every power via, to all power planes
at equal potential. This helps reduce circuit inductance. Another recommendation is to
physically locate grounds to minimize the loop area between a signal path and its
return path. Rise and fall times should be as slow as possible. Because signals with fast
rise and fall times contain many high frequency harmonics, which can radiate
significantly. The most sensitive signal returns closest to the chassis ground should be
connected together. This will result in a smaller loop area and reduce the likelihood of
crosstalk. The effect of different configurations on the amount of crosstalk can be
studied using electronics modeling software.
Signal Isolation
To maintain best signal integrity, keep digital signals far away from the analog traces. A
good rule of thumb is no digital signal should be within 300 mils (7.5 mm) of the
differential pairs. If digital signals on other board layers cannot be separated by a
ground plane, they should be routed perpendicular to the differential pairs. If there is
another LAN controller on the board, take care to keep the differential pairs from that
circuit away.
Some rules to follow for signal isolation:
• Separate and group signals by function on separate layers if possible. Keep a
• Physically group together all components associated with one clock trace to reduce
• Isolate I/O signals from high-speed signals to minimize crosstalk, which can
• Avoid routing high-speed LAN traces near other high-frequency signals associated
minimum distance between differential pairs more than seven times the dielectric
thickness away from each other and other traces, including NVM traces and parallel
digital traces.
trace length and radiation.
increase EMI emission and susceptibility to EMI from other signals.
with a video controller, cache controller, processor, or other similar devices.
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