WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 449

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Design Considerations—82574 GbE Controller
13.5.5.4
Note:
Figure 76.
Differential Pair Trace Routing for 10/100/1000 Designs
Trace routing considerations are important to minimize the effects of crosstalk and
propagation delays on sections of the board where high-speed signals exist. Signal
traces should be kept as short as possible to decrease interference from other signals,
including those propagated through power and ground planes. Observe the following
suggestions to help optimize board performance:
In manufacturing, vias are required for testing and troubleshooting purposes. The via
size should be a 17-mil (±2 mils for manufacturing variance) finished hole size (FHS).
.
Trace Routing
• Maintain constant symmetry and spacing between the traces within a differential
• Minimize the difference in signal trace lengths of a differential pair.
• Keep the total length of each differential pair under 4 inches. Although possible,
• Keep differential pairs more than seven times the dielectric thickness away from
• Keep maximum separation within differential pairs to 7 mils.
• For high-speed signals, the number of corners and vias should be kept to a
• Traces should be routed away from board edges by a distance greater than the
• Do not route traces and vias under crystals or oscillators. This will prevent coupling
pair.
designs with differential traces longer than 5 inches are much more likely to have
degraded receive Bit Error Rate (BER) performance, IEEE PHY conformance
failures, and/or excessive Electromagnetic Interference (EMI) radiation.
each other and other traces, including NVM traces and parallel digital traces.
minimum. If a 90° bend is required, it is recommended to use two 45° bends
instead. Refer to
trace height above the reference plane. This allows the field around the trace to
couple more easily to the ground plane rather than to adjacent wires or boards.
to or from the clock. And as a general rule, place traces from clocks and drives at a
minimum distance from apertures by a distance that is greater than the largest
aperture dimension
— If a LAN switch is used or the trace length from the 82574 is greater than 4
— The boosted center tap voltage is between 1.9 V dc and 2.65 V dc and
inches. It might be necessary to boost the voltage at the center tap with a
separate power supply to optimize MDI performance.
consumes up to 200 mA. Consider using a second 82574 instead of a LAN
switch and long MDI traces. It is difficult to achieve excellent performance with
long traces and analog LAN switches. An optimization effort is required to tune
the system, the center tap voltage, and magnetics modules. See
for more details.
Figure
45°
76.
45°
section 12.8
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