WG82574L S LBA9 Intel, WG82574L S LBA9 Datasheet - Page 300

• Manufacturer Part Number: WG82574L S LBA9
• Description: CONTROLLER, ENET, INTEL 82574L, 64PQFN
• Manufacturer: Intel

Specifications of WG82574L S LBA9

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

300
1. These bits are read from the NVM.
SPD_BYPS
Reserved
RO_DIS
Reserved
DMA Dynamic
Gating Enable
PHY Power
Down Enable
Reserved
Tx LS Flow
Tx LS
EIAME
Reserved
IAME
DRV_LOAD
INT_TIMERS_
CLEAR_ENA
Reserved
PBA_Supportr
Field
15
16
17
18
19
20
21
22
23
24
26:25
27
28
29
30
31
Bit(s)
0b
0b
0b
0b
0b
1b
0b
0b
0b
0b
00b
0b
0b
0b
0b
0b
Initial
Value
1
1
1
1
1
1
Speed Select Bypass
When set to 1b, all speed detection mechanisms are bypassed and
the device is immediately set to the speed indicated by CTRL.SPEED.
This provides a method for software to have full control of the speed
settings of the device as well as when the change takes place by
overriding the hardware clock switching circuitry.
Reserved
Should be set to 0b.
Relaxed Ordering Disable
When set to 1b, the device does not request any relaxed ordering
transactions regardless of the state of bit 4 (Enable Relaxed Ordering)
in the PCIe Device Control register. When this bit is cleared and bit 4
of the PCIe Device Control register is set, the device requests relaxed
ordering transactions as described in
Reserved
When set, this bit enables dynamic clock gating of the DMA and MAC
units.
When set, this bit enables the PHY to enter a low-power state.
Reserved
Should be set for correct TSO functionality. Refer to
Should be cleared for correct TSO functionality. Refer to
Extended Interrupt Auto Mask Enable
When set (usually in MSI-X mode), upon firing of an MSI-X message,
bits set in IAM associated with this message are cleared. Otherwise,
EIAM is used only upon a read of the EICR register.
Reserved
When the IAME (interrupt acknowledge auto-mask enable) bit is set,
a read or write to the ICR register has the side effect of writing the
value in the IAM register to the IMC register. When this bit is 0b, the
feature is disabled.
Driver Loaded
This bit should be set by the software device driver after it was
loaded, Cleared when the software device driver unloads or PCIe soft
reset. The Management Controller (MC) loads this bit to indicate that
the software device driver has been loaded.
When set, this bit enables the clearing of the interrupt timers
following an IMS clear. In this state, successive interrupts occur only
after the timers expire again. When cleared, successive interrupts
following IMS clear might happen immediately.
Reserved
Reads as 0b.
PBA Support
When set, setting one of the extended interrupt masks via IMS causes
the PBA bit of the associated MSI-X vector to be cleared. Otherwise,
the 82574 behaves in a way supporting legacy INT-x interrupts.
Should be cleared when working in INT-x or MSI mode and set in MSI-
X mode.
82574 GbE Controller—Driver Programing Interface
Description
Section
3.1.3.8.2.
Section
Section
7.3.
7.3.