WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 101

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
FREQUENCY LOCKED LOOP (FLL)
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DIGITAL MICROPHONE (DMIC) OPERATION
When GPIO1/DMIC_LR is configured as DMIC_LR Clock output, the WM8903 outputs a clock which
supports Digital Microphone operation at a multiple of the ADC sampling rate. The precise clock
frequency varies according to the MCLK frequency, the SAMPLE_RATE field and other settings. The
clock frequency is always within the range 1MHz - 3MHz, and some examples are shown in Table
66.
Table 66 Digital Microphone Clock
Note that the 88.2kHz and 96kHz sample rate settings are not valid for Digital Microphone operation.
The integrated FLL can be used to generate CLK_SYS from a wide variety of different reference
sources and frequencies. The FLL can use either MCLK, BCLK or LRC as its reference, which may
be a high frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz) reference. The FLL is
tolerant of jitter and may be used to generate a stable CLK_SYS from a less stable input signal. The
FLL characteristics are summarised in “Electrical Characteristics”.
Note that the FLL can be used to generate a free-running clock in the absence of an external
reference source. This is described in the “Free-Running FLL Clock” section below.
The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is
recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other
register settings have been updated. When changing the input reference frequency F
recommended the FLL be reset by setting FLL_ENA to 0.
The FLL_CLK_SRC field allows MCLK, BCLK or LRC to be selected as the input reference clock.
The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK, BCLK or LRC)
by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For best
performance, it is recommended that the highest possible frequency - within the 13.5MHz limit -
should be selected.
The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only
the default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should
be set to the recommended value quoted in Table 69.
The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid in Fractional Mode
when enabled by the field FLL_FRAC.
It is recommended that fractional Mode (FLL_FRAC = 1) is selected at all times. Power consumption
in the FLL is reduced in integer mode; however, the performance may also be reduced, with
increased noise or jitter on the output.
SAMPLE
44.1kHz
44.1kHz
16kHz
16kHz
48kHz
48kHz
32kHz
24kHz
12kHz
RATE
8kHz
8kHz
11.2896MHz
12.288MHz
12.288MHz
12.288MHz
CLK_SYS
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
CLK_SYS
1536fs
1500fs
1000fs
RATIO
768fs
750fs
256fs
250fs
256fs
272fs
375fs
500fs
FREQUENCY
2.048MHz
1.536MHz
2.822MHz
3.000MHz
2.400MHz
1.024MHz
1.200MHz
2.400MHz
2.400MHz
2.400MHz
1.500MHz
DMIC_LR
PD, Rev 4.0, September 2010
DMIC_LR RATIO
128fs
150fs
128fs
150fs
100fs
125fs
32fs
50fs
64fs
68fs
75fs
WM8903
REF
, it is
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