WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 158

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
R84 (54h)
DC Servo
Readback 4
Register 54h DC Servo Readback 4
R90 (5Ah)
Analogue HP
0
w
REGISTER
REGISTER
ADDRESS
ADDRESS
BIT
7:0
BIT
7
6
5
4
3
2
1
DCS_LOUTR_INTEG [7:0]
HPR_RMV_SHORT
HPL_RMV_SHORT
HPR_ENA_OUTP
HPL_ENA_OUTP
HPR_ENA_DLY
HPL_ENA_DLY
HPL_ENA
LABEL
LABEL
DEFAULT
0
0
0
0
0
0
0
0000_0000 Readback value on Right Line Output
DEFAULT
Removes HPL short
0 = HPL short enabled
1 = HPL short removed
For normal operation, this bit should be set as the
final step of the HPL Enable sequence.
Enables HPL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1
after the DC offset cancellation has been
scheduled.
Enables HPL intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1
after the output signal path has been configured,
and before DC offset cancellation is scheduled.
This bit should be set with at least 20us delay after
HPL_ENA.
Enables HPL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the
first step of the HPL Enable sequence.
Removes HPR short
0 = HPR short enabled
1 = HPR short removed
For normal operation, this bit should be set as the
final step of the HPR Enable sequence.
Enables HPR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1
after the DC offset cancellation has been
scheduled.
Enables HPR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to 1
after the output signal path has been configured,
and before DC offset cancellation is scheduled.
This bit should be set with at least 20us delay after
HPR_ENA.
Servo.
Two’s complement format.
LSB is 0.25mV.
Range is +/-32mV
DESCRIPTION
DESCRIPTION
PD, Rev 4.0, September 2010
Production Data
158