WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 107

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
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The WM8903 provides five multi-function pins which can be configured to provide a number of
different functions. These are digital input/output pins on the DBVDD power domain. The GPIO pins
are:
•
•
•
•
•
Each general purpose I/O pin can be configured to be a GPIO input or configured as one of a
number of output functions. Signal de-bouncing can be selected on GPIO input pins for use with
jack/button detect applications. Table 71 lists the functions that are available on each of these pins.
The default function is highlighted for each pin.
Table 71 GPIO Functions Available
The register fields that control the functionality of these pins are described in Table 72. For each pin,
the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1 to 5).
Note that the INTERRUPT pin is also referred to as GPIO4; the BCLK pin is also referred to as
GPIO5.
The pin direction, set by GPn_DIR, must be set according to the function selected by GPn_FN.
The characteristics of any pin selected as an output may be controlled by setting GPn_OP_CFG - an
output pin may be either CMOS or Open-Drain. When a pin is configured as a GPIO output, its level
can be set to logic 0 or logic 1 using the GPn_LVL field.
A pin configured as a GPIO input can be used to trigger an Interrupt event. This input may be
configured as active high or active low using the GPn_IP_CFG field. De-bouncing of this input may
be enabled using the GPn_DB field. Internal pull-up and pull-down resistors may be enabled using
the GPn_PU and GPn_PD fields. (Note that if GPn_PU and GPn_PD are both set for any GPIO pin,
then the pull-up and pull-down will be disabled.)
Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an
Interrupt event. The register field GPn_INTMODE selects edge detect or level detect Interrupt
functionality. Edge detect raises an interrupt on rising and falling transitions. Level detect asserts the
interrupt for as long as the GPIO status is asserted. See “Interrupts”.
The Digital Microphone Interface and MICBIAS Current Detect functions are described in the
“Analogue Input Signal Path” section.
GPIO Pin Function
GPIO output
BCLK input/output
Interrupt output (IRQ)
Digital Microphone Clock (DMIC_LR)
Digital Microphone Data (DMIC_DAT)
GPIO input
(including jack/button detect)
MICBIAS Current detect output
MICBIAS Short Circuit detect output
FLL Lock output
FLL Clock output
GPIO1/DMIC_LR
GPIO2/DMIC_DAT
GPIO3/ADDR
INTERRUPT (GPIO4)
BCLK (GPIO5)
GPIO1/D
MIC_LR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
MIC_DAT
GPIO2/D
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
GPIO3/
ADDR
GPIO PINS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
PD, Rev 4.0, September 2010
INTERRUPT
(GPIO4)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
WM8903
(GPIO5)
BCLK
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
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