WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 127

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
The POR
threshold has been exceeded, POR
writes to the control interface are ignored. Once AVDD and DCVDD have reached their respective
power on thresholds, POR
control interface may take place.
Note that a minimum power-on reset period, T
time. (This specification is guaranteed by design rather than test.)
On power down, POR
power-down thresholds.
Typical Power-On Reset parameters for the WM8903 are defined in Table 81.
Table 81 Typical Power-On Reset parameters
Notes:
1.
2.
3.
4.
SYMBOL
V
V
V
V
V
T
pora_on
pora_off
pord_on
pord_off
If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating
level but do not go below V
operation when the voltage is back to the recommended level again.
The chip enters reset at power down when AVDD or DCVDD falls below V
may be important if the supply is turned on and off frequently by a power management system.
The minimum t
specification is guaranteed by design rather than test.
See “Control Interface” section for details of t
¯ ¯ ¯
POR
pora
signal is undefined until AVDD has exceeded the minimum threshold, V
AVDD threshold below which POR is undefined
Power-On threshold (AVDD)
Power-Off threshold (AVDD)
Power-On threshold (DCVDD)
Power-Off threshold (DCVDD)
Minimum Power-On Reset period
¯ ¯ ¯
por
¯ ¯ ¯ is released high, all registers are in their default state, and writes to the
is asserted low when any of AVDD or DCVDD falls below their respective
period is maintained even if DCVDD and AVDD have zero rise time. This
¯ ¯ ¯ is asserted low and the chip is held in reset. In this condition, all
pora_off
DESCRIPTION
or V
pord_off
POR
) then the chip does not reset and resumes normal
pusetup
, applies even if AVDD and DCVDD have zero rise
and t
puhold
.
PD, Rev 4.0, September 2010
1.15
1.12
0.57
0.56
10.6
TYP
0.5
pora_off
UNIT
μs
V
V
V
V
V
or V
pora
WM8903
pord_off
Once this
. This
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