WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 98

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
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The CLK_SYS control register fields are defined in Table 61.
Table 61 MCLK and CLK_SYS Control
CONTROL INTERFACE CLOCKING
Register map access is possible with or without a Master Clock (MCLK). However, if CLK_SYS_ENA
has been set to 1, then a Master Clock must be present for control register Read/Write operations. If
CLK_SYS_ENA = 1 and MCLK is not present, then register access will be unsuccessful. (Note that
read/write access to register R22, containing CLK_SYS_ENA, is always possible.)
If it cannot be assured that MCLK is present when accessing the register map, then it is required to
set CLK_SYS_ENA = 0 to ensure correct operation.
It is possible to use the WM8903 analogue bypass paths to the differential line outputs (LON/LOP
and RON/ROP) without MCLK. Note that MCLK is always required when using HPOUTL, HPOUTR,
LINEOUTL or LINEOUTR.
AUTOMATIC CLOCKING CONFIGURATION
The WM8903 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The
Automatic Clocking Configuration mode simplifies the configuration of the clock dividers in the
WM8903 by deriving most of the necessary parameters from a minimum number of user registers.
The SAMPLE_RATE field selects the sample rate, fs, of the ADC and DAC. Note that the same
sample rate always applies to the ADC and DAC.
The CLK_SYS_RATE and CLK_SYS_MODE fields must be set according to the ratio of CLK_SYS
to fs. (Note that the internal clock CLK_SYS is derived from MCLK as controlled by MCLKDIV2).
When these fields are set correctly, the Sample Rate Decoder circuit automatically determines the
clocking configuration for all other circuits within the WM8903.
R20 (14h)
Clock Rates 0
R21 (15h)
Clock Rates 1
R22 (16h)
Clock Rates 2
R108 (6Ch)
Write
Sequencer 0
REGISTER
ADDRESS
BIT
15
0
2
1
0
8
MCLKDIV2
CLK_SRC_SEL
CLK_SYS_ENA
CLK_DSP_ENA
TO_ENA
WSMD_CLK_E
NA
LABEL
DEFAULT
0
0
0
0
0
0
Enables divide by 2 on MCLK
0 = CLK_SYS = MCLK
1 = CLK_SYS = MCLK / 2
SYSCLK Source Select
0 = MCLK
1 = FLL output
System Clock enable
0 = Disabled
1 = Enabled
DSP Clock enable
0 = Disabled
1 = Enabled
Zero Cross timeout enable
0 = Disabled
1 = Enabled
Write Sequencer / Mic Detect Clock
Enable.
0 = Disabled
1 = Enabled
PD, Rev 4.0, September 2010
DESCRIPTION
Production Data
98