WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 159

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
Register 5Ah Analogue HP 0
R94 (5Eh)
Analogue
Lineout 0
w
REGISTER
REGISTER
ADDRESS
ADDRESS
BIT
BIT
7
6
5
4
3
2
1
0
LINEOUTL_RMV_SHORT
LINEOUTR_RMV_SHOR
LINEOUTR_ENA_OUTP
LINEOUTL_ENA_OUTP
LINEOUTR_ENA_DLY
LINEOUTL_ENA_DLY
LINEOUTL_ENA
HPR_ENA
LABEL
LABEL
T
DEFAULT
0
DEFAULT
0
0
0
0
0
0
0
Enables HPR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the
first step of the HPR Enable sequence.
Removes LINEOUTL short
0 = LINEOUTL short enabled
1 = LINEOUTL short removed
For normal operation, this bit should be set as
the final step of the LINEOUTL Enable
sequence.
Enables LINEOUTL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to
1 after the DC offset cancellation has been
scheduled.
Enables LINEOUTL intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to
1 after the output signal path has been
configured, and before DC offset cancellation
is scheduled. This bit should be set with at
least 20us delay after LINEOUTL_ENA.
Enables LINEOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as
the first step of the LINEOUTL Enable
sequence.
Removes LINEOUTR short
0 = LINEOUTR short enabled
1 = LINEOUTR short removed
For normal operation, this bit should be set as
the final step of the LINEOUTR Enable
sequence.
Enables LINEOUTR output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to
1 after the DC offset cancellation has been
scheduled.
Enables LINEOUTR intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set to
1 after the output signal path has been
configured, and before DC offset cancellation
is scheduled. This bit should be set with at
least 20us delay after LINEOUTR_ENA.
DESCRIPTION
DESCRIPTION
PD, Rev 4.0, September 2010
WM8903
159