WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 128

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
QUICK START-UP AND SHUTDOWN
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The WM8903 has the capability to perform a quick start-up and shut-down with a minimum number
of register operations. This is achieved using the Control Write Sequencer, which is configured with
default start-up settings that set up the device for DAC playback via Headphone and Line Output.
Assuming a 12.288MHz external clock, the start-up sequence configures the device for 48kHz
playback mode.
The default start-up sequence requires three register write operations. The default shutdown
sequence requires just a single register write. The minimum procedure for executing the quick start-
up and shutdown sequences is described below. See “Control Write Sequencer” for more details.
QUICK START-UP (DEFAULT SEQUENCE)
An external clock must be applied to MCLK. Assuming 12.288MHz input clock, the start-up sequence
will take approximately 425ms to complete.
The following register operations will initiate the quick start-up sequence.
Table 82 Quick Start-Up Control
The WSEQ_BUSY bit (in Register R112, see Table 76) will be set to 1 while the sequence runs.
When this bit returns to 0, the device has been set up and is ready for DAC playback operation.
QUICK SHUTDOWN (DEFAULT SEQUENCE)
The default shutdown sequence assumes the initial device conditions are as configured by the
default start-up sequence. Assuming 12.288MHz input clock, the shutdown sequence will take
approximately 325ms to complete.
The following register operation will initiate the default shut-down sequence.
Table 83 Quick Shutdown Control
The WSEQ_BUSY bit (in Register R112, see Table 76) will be set to 1 while the sequence runs.
When this bit returns to 0, the system clock can be disabled (CLK_SYS_ENA=0) and MCLK can be
stopped.
R108 (6Ch)
Write Sequencer 0
R22 (16h)
Clock Rates 2
R111 (6Fh)
Write Sequencer 3
R111 (6Fh)
Write Sequencer 3
REGISTER
REGISTER
ADDRESS
ADDRESS
VALUE
VALUE
0100h
0004h
0100h
0120h
WSMD_CLK_ENA = 1
This enables the Write Sequencer Clock
CLK_SYS_ENA = 1
This enables the System Clock
WSEQ_START_INDEX = 00h
WSEQ_START = 1
WSEQ_ABORT = 0
This starts the Write Sequencer at Index address 0 (00h)
WSEQ_START_INDEX = 20h
WSEQ_START = 1
WSEQ_ABORT = 0
This starts the Write Sequencer at Index address 32 (20h)
DESCRIPTION
DESCRIPTION
PD, Rev 4.0, September 2010
Production Data
128