WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 124

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

42 (2Ah)
43 (2Bh)
44 (2Ch)
45 (2Dh)
46 (2Eh)
32 (20h)
33 (21h)
34 (22h)
35 (23h)
36 (24h)
37 (25h)
38 (26h)
39 (27h)
40 (28h)
41 (29h)
WM8903
w
WSEQ
INDEX
REGISTER
ADDRESS
R94 (5Eh)
R90 (5Ah)
R90 (5Ah)
R94 (5Eh)
R14 (0Eh)
R15 (0Fh)
R13 (0Dh)
R67 (43h)
R98 (62h)
R18 (12h)
R22 (16h)
R4 (04h)
R5 (05h)
R5 (05h)
R5 (05h)
WIDTH
8 bits
8 bits
8 bits
8 bits
4 bits
2 bits
2 bits
2 bits
2 bits
2 bits
1 bit
1 bit
1 bit
1 bit
1 bit
SHUTDOWN SEQUENCE
The Shutdown sequence is initiated by writing 0120h to Register R111 (6Fh). This single operation
starts the Control Write Sequencer at Index Address 32 (20h) and executes the sequence defined in
Table 80.
For typical clocking configurations with MCLK=12.288MHz, this sequence takes approximately
325ms to run.
START
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 2
Bit 1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 3
Bit 0
Bit 0
DATA
77h
77h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
02h
00h
00h
DELAY
Ch
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
9h
EOS
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
(delay = 0.5625ms)
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
(delay = 0.5625ms)
HPL_ENA_OUTP = 0
HPL_ENA_DLY = 0
HPL_ENA = 0
HPR_ENA_OUTP = 0
HPR_ENA_DLY = 0
HPR_ENA = 0
(delay = 0.5625ms)
LINEOUTL_ENA_OUTP = 0
LINEOUTL_ENA_DLY = 0
LINEOUTL_ENA = 0
LINEOUTR_ENA_OUTP = 0
LINEOUTR_ENA_DLY = 0
LINEOUTR_ENA = 0
(delay = 0.5625ms)
DCS_ENA = 0000
(delay = 0.5625ms)
CP_ENA = 0
(delay = 0.5625ms)
DACL_ENA = 0
DACR_ENA = 0
(delay = 0.5625ms)
CLK_DSP_ENA = 0
(delay = 0.5625ms)
HPL_PGA_ENA = 0
HPR_PGA_ENA = 0
(delay = 0.5625ms)
LINEOUTL_PGA_ENA = 0
LINEOUTR_PGA_ENA = 0
(delay = 0.5625ms)
MIXOUTL_ENA = 0
MIXOUTR_ENA = 0
(delay = 0.5625ms)
BIAS_ENA = 0
(delay = 0.5625ms)
VMID_SOFT = 10
(delay = 0.5625ms)
VMID_BUF_ENA = 0
(delay = 256.5ms)
VMID_BUF_ENA = 0
(delay = 32.5ms)
DESCRIPTION
PD, Rev 4.0, September 2010
Production Data
124