WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 93

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
COMPANDING
The WM8903 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC)
sides as shown in Table 58.
Table 58 Companding Control
Companding uses a piecewise linear approximation of the following equations (as set out by ITU-T
G.711 standard) for data compression:
μ-law (where μ=255 for the U.S. and Japan):
A-law (where A=87.6 for Europe):
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs of
data.
Companding converts 13 bits (μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).
8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows
samples to be passed using as few as 8 BCLK cycles per LRC frame. When using DSP mode B, 8-
bit data words may be transferred consecutively every 8 BCLK cycles.
8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 or
ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0.
Table 59 8-bit Companded Word Composition
SIGN
R24 (18h)
Audio
Interface 0
BIT7
REGISTER
ADDRESS
F(x) = ln( 1 + μ|x|) / ln( 1 + μ)
F(x) = A|x| / ( 1 + lnA)
F(x) = ( 1 + lnA|x|) / (1 + lnA)
BIT
EXPONENT
3
2
1
0
BIT [6:4]
ADC_COMP
ADC_COMPMO
DE
DAC_COMP
DAC_COMPMO
DE
LABEL
DEFAULT
-1 ≤ x ≤ 1
x ≤ 1/A
1/A ≤ x ≤ 1
0
0
0
0
ADC Companding Enable
0 = disabled
1 = enabled
ADC Companding Type
0 = μ-law
1 = A-law
DAC Companding Enable
0 = disabled
1 = enabled
DAC Companding Type
0 = μ-law
1 = A-law
MANTISSA
BIT [3:0]
PD, Rev 4.0, September 2010
DESCRIPTION
WM8903
93