WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 103

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
See Table 69 for the coding of the FLL_OUTDIV and FLL_FRATIO fields.
Note that F
In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.
This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if
desired, the value of this field may be calculated by multiplying K by 2
integer value, as illustrated in the following example:
For best performance, FLL Fractional Mode should always be used. Therefore, if the calculations
yield an integer value of N.K, then it is recommended to adjust FLL_FRATIO in order to obtain a non-
integer value of N.K. Care must always be taken to ensure that the FLL operating frequency, F
within its recommended limits of 90-100 MHz.
The register fields that control the FLL are described in Table 69. Example settings for a variety of
reference frequencies and output frequencies are shown in Table 70.
R128 (80h)
FLL Control 1
R129 (81h)
FLL Control 2
REGISTER
ADDRESS
If N.K = 8.192, then K = 0.192
Multiplying K by 2
Apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex)
REF
is the input frequency, after division by FLL_CLK_REF_DIV, where applicable.
12:11
BIT
7:4
3
2
0
16
FLL_GAIN [3:0]
FLL_HOLD
FLL_FRAC
FLL_ENA
FLL_CLK_SRC
[1:0]
gives 0.192 x 65536 = 12582.912 (decimal)
LABEL
DEFAULT
0h
00
0
0
0
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that this register is not
changed from default.
FLL Hold Select
0 = Disabled
1 = Enabled
This feature enables free-running
mode in FLL when reference clock is
removed
Fractional enable
0 = Integer Mode
1 = Fractional Mode
Fractional Mode is recommended in
all cases
FLL Enable
0 = Disabled
1 = Enabled
FLL Clock source
00 = MCLK
01 = BCLK
10 = LRC
11 = Reserved
PD, Rev 4.0, September 2010
16
DESCRIPTION
and treating FLL_K as an
WM8903
VCO
103
, is