WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 65

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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HEADPHONE / LINE OUTPUT SIGNAL PATHS ENABLE
The Headphone / Line output paths can be actively discharged to AGND through internal resistors if
desired. This is desirable at start-up in order to achieve a known output stage condition prior to
enabling the VMID reference voltage. This is also desirable in shutdown to prevent the external
connections from being affected by the internal circuits. The ground-referenced Headphone outputs
and Line outputs are shorted to AGND by default; the short circuit is removed on each of these paths
by setting the applicable fields HPL_RMV_SHORT, HPR_RMV_SHORT, LINEOUTL_RMV_SHORT
or LINEOUTR_RMV_SHORT.
The ground-referenced Headphone output and Line output drivers are designed to suppress pops
and clicks when enabled or disabled. However, it is necessary to control the drivers in accordance
with a defined sequence in start-up and shut-down to achieve the pop suppression. It is also
necessary to schedule the DC Servo offset correction at the appropriate point in the sequence (see
“DC Servo”). Table 39 and Table 40 describe the recommended sequences for enabling and
disabling these output drivers.
Step 1
Step 2
Step 3
Step 4
Step 5
Table 39 Headphone / Line Output Enable Sequence
Step 1
Step 2
Table 40 Headphone / Line Output Disable Sequence
The registers relating to Headphone / Line Output pop suppression control are defined in Table 41.
R90 (5Ah)
Analogue
HP 0
REGISTER
ADDRESS
SEQUENCE
SEQUENCE
BIT
7
6
HPL_RMV_SHOR
T
HPL_ENA_OUTP
HPL_ENA = 1
HPR_ENA = 1
HPL_ENA_DLY = 1
HPR_ENA_DLY = 1
DC offset correction
HPL_ENA_OUTP = 1
HPR_ENA_OUTP = 1
HPL_RMV_SHORT = 1
HPR_RMV_SHORT = 1
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
HPL_ENA = 0
HPL_ENA_DLY = 0
HPL_ENA_OUTP = 0
HPR_ENA = 0
HPR_ENA_DLY = 0
HPR_ENA_OUTP = 0
LABEL
HEADPHONE DISABLE
HEADPHONE ENABLE
DEFAULT
0
0
Removes HPL short
0 = HPL short enabled
1 = HPL short removed
For normal operation, this bit should
be set as the final step of the HPL
Enable sequence.
Enables HPL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
LINEOUTL_ENA = 1
LINEOUTR_ENA = 1
LINEOUTL_ENA_DLY = 1
LINEOUTR_ENA_DLY = 1
DC offset correction
LINEOUTL_ENA_OUTP = 1
LINEOUTR_ENA_OUTP = 1
LINEOUTL_RMV_SHORT = 1
LINEOUTR_RMV_SHORT = 1
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
LINEOUTL_ENA = 0
LINEOUTL_ENA_DLY = 0
LINEOUTL_ENA_OUTP = 0
LINEOUTR_ENA = 0
LINEOUTR_ENA_DLY = 0
LINEOUTR_ENA_OUTP = 0
PD, Rev 4.0, September 2010
LINEOUT DISABLE
LINEOUT ENABLE
DESCRIPTION
WM8903
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