WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 105

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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FREE-RUNNING FLL CLOCK
The FLL can generate a clock signal even when the external reference is removed. It should be
noted that the accuracy of this clock is reduced, and a reference source should always be used
where possible. In free-running modes, the FLL is not sufficiently accurate for hi-fi audio applications.
The free-running modes are suitable for clocking other functions, including the Write Sequencer and
DC servo control. The free-running mode can be used to support the analogue input (bypass) audio
paths.
A clock reference is required for initial configuration of the FLL as described above. For free-running
operation, the FLL_HOLD bit should be set, as described in Table 69. When FLL_HOLD is set, the
FLL will continue to generate a stable output clock after the reference input is stopped or
disconnected.
Note that the FLL must be selected as the CLK_SYS source by setting CLK_SRC_SEL (see Table
61). Note that, in the absence of any reference clock, the FLL output is subject to a very wide
tolerance. See “Electrical Characteristics” for details of the FLL accuracy.
GPIO OUTPUTS FROM FLL
The WM8903 has an internal signal which indicates whether the FLL Lock has been achieved. The
FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt
event - see “Interrupts”.
The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See
“General Purpose Input/Output (GPIO)” for details of how to configure a GPIO pin to output the FLL
Lock signal.
The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the
FLL Clock may be output even if the FLL is not selected as the WM8903 CLK_SYS source. The
clocking configuration is illustrated in Figure 55. See “General Purpose Input/Output (GPIO)” for
details of how to configure a GPIO pin to output the FLL Clock.
EXAMPLE FLL CALCULATION
To generate 12.288 MHz output (F
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Set FLL_CLK_REF_DIV in order to generate F
FLL_CLK_REF_DIV = 00 (divide by 1)
Set FLL_CTRL_RATE to the recommended setting:
FLL_CTRL_RATE = 000 (divide by 1)
Set FLL_GAIN to the recommended setting:
FLL_GAIN = 0000 (multiply by 1)
Set FLL_OUTDIV for the required output frequency as shown in Table 67:-
F
Set FLL_FRATIO for the given reference frequency as shown in Table 68:
F
Calculate F
F
Calculate N.K as given by N.K = F
N.K = 98.304 / (1 x 12) = 8.192
Determine FLL_N and FLL_K from the integer and fractional portions of N.K:-
FLL_N is 8. FLL_K is 0.192
Confirm that N.K is a fractional quantity and set FLL_FRAC:
N.K is fractional. Set FLL_FRAC = 1.
Note that, if N.K is an integer, then an alternative value of FLL_FRATIO should be
selected in order to produce a fractional value of N.K.
OUT
REF
VCO
= 12MHz, therefore FLL_FRATIO = 0h (divide by 1)
= 12.288 MHz, therefore FLL_OUTDIV = 2h (divide by 8)
= 12.288 x 8 = 98.304MHz
VCO
as given by F
OUT
) from a 12.000 MHz reference clock (F
VCO
= F
VCO
OUT
/ (FLL_FRATIO x F
x FLL_OUTDIV:-
REF
<=13.5MHz:
REF
PD, Rev 4.0, September 2010
):
REF
):
WM8903
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