WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 41

no-image

WM8903LGEFK/RV

Manufacturer Part Number
WM8903LGEFK/RV
Description
Audio CODECs ULTRA LOW PWR HI FI CODEC
Manufacturer
Wolfson Microelectronics
Datasheets

Specifications of WM8903LGEFK/RV

Audio Codec Type
Stereo Codec
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
6
No. Of Output Channels
8
Adc / Dac Resolution
24bit
Sampling Rate
96kHz
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Adcs / Dacs Signal To Noise Ratio
96dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM8903LGEFK/RV
Manufacturer:
SHARP
Quantity:
93
Part Number:
WM8903LGEFK/RV
Quantity:
2 386
Part Number:
WM8903LGEFK/RV
Manufacturer:
WOFLSON
Quantity:
20 000
Part Number:
WM8903LGEFK/RVA
Manufacturer:
SHARP
Quantity:
709
Part Number:
WM8903LGEFK/RVA
Manufacturer:
WOFLSON
Quantity:
20 000
Production Data
Figure 28 Digital Microphone Interface Control
w
When GPIO1 is configured as DMIC_LR Clock output, the WM8903 outputs a clock which supports
Digital Mic operation at a multiple of the ADC sampling rate, in the range 1-3MHz. The ADC and
Record Path filters must be enabled and the ADC sampling rate must be set in order to ensure
correct operation of all DSP functions associated with the digital microphone. Volume control for the
Digital Microphone Interface signals is provided using the ADC Volume Control.
See “Analogue-to-Digital Converter (ADC)” for details of the ADC Enable and volume control
functions. See “General Purpose Input/Output (GPIO)” for details of configuring the DMIC_LR and
DMIC_DAT functions. See “Clocking and Sample Rates” for the details of the supported clocking
configurations.
When GPIO2/DMIC_DAT is configured as DMIC_DAT input, then this pin is the digital microphone
input. Up to two microphones can share this pin; the two microphones are interleaved as illustrated in
Figure 29.
The digital microphone interface requires that MIC1 transmits a data bit each time that DMIC_LR is
high, and MIC2 transmits when DMIC_LR is low. The WM8903 samples the digital microphone data
in the middle of each DMIC_LR clock phase. Each microphone must tri-state its data output when
the other microphone is transmitting.
Figure 29 Digital Microphone Interface Timing
The digital microphone interface control fields are described in Table 9.
PD, Rev 4.0, September 2010
WM8903
41

Related parts for WM8903LGEFK/RV