LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet

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... Programmable rate limiting at the ingress with coloring and random early discard, per port / priority – Programmable rate limiting at the egress with leaky bucket algorithm, per port / priority SMSC LAN9303M/LAN9303Mi LAN9303M/LAN9303Mi Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII — ...

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... LAN9303M-AKZE FOR 72-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE) LAN9303Mi-AKZE FOR 72-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO 85°C TEMP RANGE) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...

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... Port 1 & 2 PHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2.1 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2.2 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2.3 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.4 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.5 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.6 Device Ready Interrupt SMSC LAN9303M/LAN9303Mi 3 DATASHEET Revision 1.4 (07-07-10) ...

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... Phase Lock Loop (PLL) ........................................................................................................................................................................ 99 7.2.2 100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.2.2.1 A/D Converter ............................................................................................................................................................................................... 100 7.2.2.2 DSP: Equalizer, BLW Correction and Clock/Data Recovery ........................................................................................................................ 100 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 4 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

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... MAC Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.4.4 Soft-Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.4.4.1 PHY Registers Synchronization.................................................................................................................................................................... 122 8.4.4.2 Virtual PHY Registers Synchronization......................................................................................................................................................... 123 8.4.4.3 Port 1 MII Basic Control Register Synchronization ....................................................................................................................................... 123 8.4.4.4 LED and Manual Flow Control Register Synchronization ............................................................................................................................. 123 SMSC LAN9303M/LAN9303Mi 5 DATASHEET Revision 1.4 (07-07-10) ...

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... General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.2 Free-Running Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Chapter 12 GPIO/LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2 GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.2.1 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 6 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

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... Switch Device ID Register (SW_DEV_ID) .................................................................................................................................................... 237 13.4.1.2 Switch Reset Register (SW_RESET) ........................................................................................................................................................... 238 13.4.1.3 Switch Global Interrupt Mask Register (SW_IMR)........................................................................................................................................ 239 13.4.1.4 Switch Global Interrupt Pending Register (SW_IPR).................................................................................................................................... 240 13.4.2 Switch Port 0, Port 1, and Port 2 CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SMSC LAN9303M/LAN9303Mi 7 DATASHEET Revision 1.4 (07-07-10) ...

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... Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) ........................................... 323 13.4.3.35 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2) ........................................... 324 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 8 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

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... Turbo MII Interface Timing (PHY Mode 373 14.5.8 RMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 14.5.9 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 14.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Chapter 15 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15.1 72-QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Chapter 16 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 SMSC LAN9303M/LAN9303Mi 9 DATASHEET Revision 1.4 (07-07-10) ...

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... Figure 14.13RMII Px_OUTCLK Input Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Figure 14.14SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Figure 15.1 72-QFN Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Figure 15.2 72-QFN Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 10 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

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... Table 3.8 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 3.9 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 3.10 Core and I/O Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 3.11 LAN9303M/LAN9303Mi 72-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 3.12 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 4.1 Reset Sources and Affected Device Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 4.2 Soft-Strap Configuration Strap Definitions Table 4 ...

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... Table 14.18RMII Px_OUTCLK Input Mode Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Table 14.19SMI Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Table 14.20Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Table 15.1 72-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Table 16.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 12 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

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... Level-Triggered Sticky Bit lsb LSB MDI MDIX MII MIIM SMSC LAN9303M/LAN9303Mi 10BASE-T (10Mbps Ethernet, IEEE 802.3) 100BASE-TX (100Mbps Fast Ethernet, IEEE 802.3u) Analog-to-Digital Converter Address Logic Resolution Baseline Wander Buffer Manager - Part of the switch fabric Bridge Protocol Data Unit - Messages which carry the Spanning Tree ...

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... Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an Ethernet frame. Serial In Parallel Out Serial Management Interface Signal Quality Error (also known as “heartbeat”) Start of Stream Delimiter User Datagram Protocol - A connectionless protocol run on top of IP networks Universally Unique IDentifier 16-bits 14 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

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... Switch Fabric are managed via the Switch Fabric configuration and status registers, which are indirectly accessible via the system control and status registers. The LAN9303M/LAN9303Mi provides 3 switched ports. Each port is fully compliant with the IEEE 802.3 standard and all internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation ...

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... PHY or MII/RMII/ Turbo MII to MAC 10/100 Mode Configuration Straps MAC MII Ethernet 10/100 PHY MDIO Registers GPIO/LED Controller LAN9303M/ LAN9303Mi To optional GPIOs/LEDs MII/Turbo MII to PHY or MII/RMII/Turbo MII to MAC MII 10/100 Data MAC Path Search Switch Engine Engine Mode Configuration Buffer Manager Frame ...

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... Quality of Service (QoS) packet prioritization by VLAN tag, destination address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. A 512 entry forwarding table provides ample room for MAC address forwarding tables. SMSC LAN9303M/LAN9303Mi Operation"). Each 10/100 MAC includes RX and TX FIFOs 17 DATASHEET ...

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... C-Bus Specification. A list of management modes and configurations settings Section 2.3, "Modes of Operation" master module which interfaces an optional external EEPROM with 2 C-Bus Specification. 18 DATASHEET Datasheet Operation"). The PMI 2 C slave serial interface (start and stop 2 C slave controller Section 2.3, "Modes SMSC LAN9303M/LAN9303Mi ...

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... Modes of Operation The LAN9303M/LAN9303Mi is designed to integrate into various embedded environments. To accomplish compatibility with a wide range of applications, the LAN9303M/LAN9303Mi ports can operate in the following modes: Port 0 - Independently configured for MII MAC, MII PHY, RMII PHY modes Port 1 - Independently configured for internal PHY, MII MAC, MII PHY, RMII PHY modes ...

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... Figure 2.3 MII/RMII PHY Mode 2 C interface or the SMI/MIIM (Media Independent 2 C slave. The slave mode is used as a register access path for master EEPROM interface are shared interfaces. 20 DATASHEET Datasheet EEPROM (optional managed as detailed EEPROM C slave (optional) 2 C). The slave SMSC LAN9303M/LAN9303Mi ...

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... I C master used to load initial configuration from EEPROM and for CPU R/W access to EEPROM slave used for management SMSC LAN9303M/LAN9303Mi Table 2.1. System configuration diagrams for each mode are Table 2.1 Device Modes SMI/MIIM P0_MODE[2:0] INTERFACE STRAP VALUE SMI/MIIM slave, 000 ...

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... LAN9303M/LAN9303Mi MAC Modes SMI Managed LAN9303M/ Ethernet LAN9303Mi Magnetics EEPROM slave Ethernet Magnetics MIIM/ MII SMI MII MIIM Ethernet 10/100 Magnetics PHY Managed LAN9303M/ Ethernet LAN9303Mi Magnetics EEPROM slave Ethernet Magnetics MIIM/ MII SMI MII MIIM Ethernet 10/100 Magnetics PHY Figure 2.4 Port 0 MAC/PHY Management Modes Revision 1 ...

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... VDD33A2 69 TXP2 70 TXN2 71 P0_IND3 72 NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground SMSC LAN9303M/LAN9303Mi SMSC 72 PIN QFN (TOP VIEW) VSS Figure 3.1 Pin Assignments (TOP VIEW) 23 DATASHEET P1_COL 36 ...

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... Serial Management/EEPROM Pins Miscellaneous Pins PLL Pins Core and I/O Power and Ground Pins Note: A list of buffer type definitions is provided in Note: Please refer to the LAN9303M/LAN9303Mi Reference Schematic and LANCheck Schematic Checklist on the SMSC website for additional connection information. NUM PINS NAME ...

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... Transmitter +1.8V Power 1 Supply Port 1 VDD18TX1 Transmitter 1 +1.8V Power Supply Note 3.3 Please refer to the LAN9303M/LAN9303Mi Reference Schematic and LANCheck Schematic Checklist on the SMSC website for additional connection information. NUM PINS NAME SYMBOL Port 1 MII Input 1 P1_IND3 Data 3 SMSC LAN9303M/LAN9303Mi BUFFER ...

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... MAC to the switch. The pull-down (PD) and input buffer are disabled when the set in the Port 1 MII Basic Control Register (P1_MII_BASIC_CONTROL). (PD) Internal PHY Mode: This pin is not used. 26 DATASHEET Datasheet DESCRIPTION Isolate bit is Isolate bit is Isolate bit is Isolate bit is Isolate bit is SMSC LAN9303M/LAN9303Mi ...

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... Data Valid Port 1 MII Input 1 P1_INER Error Port 1 MII Input 1 Reference P1_INCLK Clock SMSC LAN9303M/LAN9303Mi BUFFER TYPE DESCRIPTION IS MII MAC Mode: This pin is the RX_DV signal from the external PHY and indicates valid data on (PD) P1_IND[3:0] and P1_INER. IS MII PHY Mode: This pin is the TX_EN signal from ...

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... See Note 3.4. (PU) Note 3.5 Please refer to the mode encoding details. 28 DATASHEET Datasheet DESCRIPTION Isolate bit is set in the 3.4. Isolate bit is set in the P1_MODE0 strap entry for Isolate bit is set in the Isolate bit is set in the P1_MODE0 strap entry for SMSC LAN9303M/LAN9303Mi ...

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... Port 1 Mode[0] P1_MODE0 Configuration Strap Port 1 MII 1 Output Data P1_OUTDV Valid SMSC LAN9303M/LAN9303Mi BUFFER TYPE DESCRIPTION O8 MII MAC Mode: This pin is the transmit data 0 bit from the switch to the external PHY. O8 MII PHY Mode: This pin is the receive data 0 bit from the switch to the external MAC. The output ...

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... Internal PHY Mode: This pin is not used. 30 DATASHEET Datasheet DESCRIPTION Isolate bit is set in the Port 1 MII RMII/Turbo MII Clock Strength bit bit in the Port 1 MII Basic (P1_MII_BASIC_CONTROL). A Port 1 MII Basic Control RMII/Turbo MII Clock Strength bit Isolate bit is set Isolate bit is set in the Port 1 SMSC LAN9303M/LAN9303Mi ...

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... MAC/PHY device. NUM PINS NAME SYMBOL Port 0 MII Input 1 P0_IND3 Data 3 SMSC LAN9303M/LAN9303Mi BUFFER TYPE IS MII MAC Mode: This pin is an input from the external PHY indicating a network carrier. (PD) O8 MII PHY Mode: This pin is an output to the external MAC indicating a network carrier ...

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... Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). 32 DATASHEET Datasheet DESCRIPTION Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate (VPHY_ISO) bit is set in SMSC LAN9303M/LAN9303Mi ...

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... Clock Port 0 MII P0_OUTD3 Output Data 3 1 Port 0 Duplex DUPLEX_POL_0 Polarity Configuration Strap SMSC LAN9303M/LAN9303Mi BUFFER TYPE DESCRIPTION IS MII MAC Mode: This pin is the RX_ER signal from the external PHY and indicates a receive error in (PD) the packet. IS MII PHY Mode: This pin is the TX_ER signal from ...

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... IS This strap configures the mode for Port 0. See Note 3.6. (PU) Note 3.7 Please refer to the mode encoding details. 34 DATASHEET Datasheet DESCRIPTION Isolate (VPHY_ISO) bit P0_MODE0 strap entry for Isolate (VPHY_ISO) bit Isolate (VPHY_ISO) bit P0_MODE0 strap entry for SMSC LAN9303M/LAN9303Mi ...

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... Port 0 Mode[0] P0_MODE0 Configuration Strap Port 0 MII 1 Output Data P0_OUTDV Valid SMSC LAN9303M/LAN9303Mi BUFFER TYPE DESCRIPTION O8 MII MAC Mode: This pin is the transmit data 0 bit from the switch to the external PHY. O8 MII PHY Mode: This pin is the receive data 0 bit from the switch to the external MAC. The output ...

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... RMII PHY Mode: This pin is not used. 36 DATASHEET Datasheet DESCRIPTION Isolate (VPHY_ISO) bit is set in RMII/Turbo MII Clock Strength bit bit in the Virtual PHY Special bit is set in the Virtual PHY (VPHY_BASIC_CTRL). RMII/Turbo MII Clock Strength bit is set in the Isolate (VPHY_ISO) bit is set SMSC LAN9303M/LAN9303Mi ...

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... EEPROM Loader. Please refer to on page 51 Note 3.7 An external supplemental pull-up may be needed, depending upon the input current loading of the external MAC/PHY device. SMSC LAN9303M/LAN9303Mi BUFFER TYPE IS MII MAC Mode: This pin is an input from the external PHY indicating a network carrier. ...

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... LED to VDD is used as the pull-up. 38 DATASHEET Datasheet DESCRIPTION LED Configuration is set. The buffer type LED Function 1-0 LED Configuration and is configured to be either strap value sampled at reset. LED Configuration is clear. The pin is fully and the General Purpose (GPIO_DATA_DIR). SMSC LAN9303M/LAN9303Mi ...

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... LED 4 LED4 GPIO 4 GPIO4 1 Serial MNGT1_LED4P Management Mode[1] and LED 4 Polarity Configuration Strap SMSC LAN9303M/LAN9303Mi BUFFER TYPE DESCRIPTION O12/ This pin is configured to operate as an LED when the LED 4 Enable bit in the OD12/ Register (LED_CFG) OS12 depends on the setting of the (LED_FUN[1:0]) field in the ...

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... The LED is set as active low, since it is assumed that a LED to VDD is used as the pull-up. 40 DATASHEET Datasheet DESCRIPTION LED Configuration is set. The buffer type LED Function 1-0 LED Configuration and is configured to be either LED Configuration is clear. The pin is fully and the General Purpose (GPIO_DATA_DIR). SMSC LAN9303M/LAN9303Mi ...

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... SYMBOL LED 2 LED2 GPIO 2 GPIO2 1 EEPROM Size E2PSIZE_LED2P and LED 2 Polarity Configuration Strap SMSC LAN9303M/LAN9303Mi BUFFER TYPE DESCRIPTION O12/ This pin is configured to operate as an LED when the LED 2 Enable bit in the OD12/ Register (LED_CFG) OS12 depends on the setting of the (LED_FUN[1:0]) field in the ...

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... LED to VDD is used as the pull-up. 42 DATASHEET Datasheet DESCRIPTION LED Configuration is set. The buffer type LED Function 1-0 LED Configuration and is configured to be either strap value sampled at reset. LED Configuration is clear. The pin is fully and the General Purpose (GPIO_DATA_DIR). Note 3.8. SMSC LAN9303M/LAN9303Mi ...

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... They are described in values from the EEPROM Loader. Please refer to page 51 for further information. SMSC LAN9303M/LAN9303Mi BUFFER TYPE O12/ This pin is configured to operate as an LED when the LED 0 Enable bit in the ...

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... This pin must be pulled- external resistor at all times clock input/open-drain This pin must be pulled- external resistor at all times clock input This pin must be pulled- external resistor at all times. for additional information DESCRIPTION Interrupt Configuration (IRQ_CFG). Please refer to Chapter 5, for further details. 365. SMSC LAN9303M/LAN9303Mi ...

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... Power Supply Output 2 1 Common PAD Ground Note 3.10 Please refer to the LAN9303M/LAN9303Mi Reference Schematic and LANCheck Schematic Checklist on the SMSC website for additional connection information. SMSC LAN9303M/LAN9303Mi Table 3.9 PLL Pins BUFFER TYPE P This pin must be connected to VDD18CORE for proper operation ...

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... Table 3.11 LAN9303M/LAN9303Mi 72-QFN Package Pin Assignments PIN PIN NUM PIN NAME NUM 1 P0_IND2 19 2 P0_IND1 20 3 P0_IND0 21 4 P0_INDV 22 5 P0_INER 23 6 P0_INCLK 24 7 VDD33IO 25 8 VDD18CORE 26 9 P0_OUTD3/ 27 DUPLEX_POL_0 10 P0_OUTD2/ 28 P0_MODE2 11 P0_OUTD1/ 29 P0_MODE1 12 P0_OUTD0/ 30 P0_MODE0 13 P1_IND3 31 14 P1_IND2 32 15 ...

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... When connected to a load that must be pulled low, an external resistor must be added. AI Analog input AIO Analog bi-directional ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin P Power pin SMSC LAN9303M/LAN9303Mi Table 3.12 Buffer Types DESCRIPTION 47 DATASHEET Revision 1.4 (07-07-10) ...

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... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII Section 14.6, "Clock Circuit," on page for additional details. Table 14.20, “Crystal Specifications,” on page for detailed information on the usage of these straps. for additional information. 48 DATASHEET Datasheet 378. Optionally, this clock can Chapter 11, "General Purpose 378. SMSC LAN9303M/LAN9303Mi ...

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... Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of this reset input is optional, but when used, it must be driven for the period of time specified in Section 14.5.2, "Reset and Configuration Strap Timing," on page are latched, and the EEPROM Loader is run as a result of this reset. SMSC LAN9303M/LAN9303Mi ...

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... Datasheet for a description of the nRST pin. Byte Order Test Device Ready until it is set. When set, the Device (HW_CFG), Byte Order Test Register bit of the Reset Control bit of the Reset Control Port x PHY Basic Control Register Port 2 PHY Reset SMSC LAN9303M/LAN9303Mi ...

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... EEPROM Loader, while hard-straps cannot. Configuration straps which have a corresponding external pin include internal resistors in order to prevent the signal from floating when unconnected particular configuration strap is connected to SMSC LAN9303M/LAN9303Mi Section 7.2.9, "PHY Power-Down Modes," on page 107 or the Reset (PHY_RST) until it clears ...

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... Section 8.4, "EEPROM Loader," on page 120 Table 4.2 means the register bit is loaded with the strap value, while the bit in the Reset Control Register (RESET_CTL) EEPROM Command Register 52 DATASHEET Datasheet 365. Chapter 3, "Pin Description and for information on or upon (E2P_CMD), these straps return SMSC LAN9303M/LAN9303Mi ...

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... Refer to the respective register definition sections for additional information. SQE_test_disable_strap_1 Configures the default value of the 1 MII Basic Control Register (P1_MII_BASIC_CONTROL) when in MII PHY mode not used in internal PHY, RMII PHY, or MII MAC mode. SMSC LAN9303M/LAN9303Mi bits of the (LED_CFG). bits of the (LED_CFG). AMDIX_EN Strap State Port 1 (HW_CFG). ...

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... Port 1 Backpressure Enable bit of the Port 1 Manual Flow Control Register 54 DATASHEET Datasheet PIN / DEFAULT VALUE 1b Port 1 MII bit of the bits of 1b when in internal PHY mode (P1_MODE[2:0] = 111b) else Duplex Mode bit DUPLEX_POL_1 when in MII PHY, RMII PHY, or MII MAC mode 1b SMSC LAN9303M/LAN9303Mi ...

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... Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1) for Port 2 when the auto_mdix_strap_2 is low and the MDIX Control (AMDIXCTRL) Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) strap settings are to be used for auto-MDIX configuration. SMSC LAN9303M/LAN9303Mi and Port 1 Full-Duplex Receive Flow Control bits of the Port 1 Manual Flow Control bit of the ...

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... Port x PHY Basic bit of the Port x PHY Auto- bits of the Port x PHY Special Port 2 Backpressure Enable bit of the Port 2 Manual Flow Control Register 56 DATASHEET Datasheet PIN / DEFAULT VALUE 1b enable bit and Duplex bits of 1b bit of the bit 1b 1b SMSC LAN9303M/LAN9303Mi ...

Page 57

... Ability Register 100BASE-X Full Duplex 100BASE-X Half Duplex 10BASE-T Full Duplex 10BASE-T Half Duplex Refer to information. SMSC LAN9303M/LAN9303Mi and Port 2 Full-Duplex Receive Flow Control bits of the Port 2 Manual Flow Control . bit of the Port x PHY Auto-Negotiation Port 2 Full-Duplex Manual Flow Control ...

Page 58

... Virtual PHY is not applicable, and full-duplex flow control must be controlled manually by the host, based upon the external PHYs Auto- negotiation results. SQEOFF bit of the Virtual PHY Special when in MII PHY 58 DATASHEET Datasheet PIN / DEFAULT VALUE Table 4.3 provides a list of 23. SMSC LAN9303M/LAN9303Mi ...

Page 59

... Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS). turbo_mii_enable_strap_0 Port 0 Turbo MII Enable Strap: Configures the default value of the Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) mode. SMSC LAN9303M/LAN9303Mi DESCRIPTION 2 C Managed Mode Section 2.3, "Modes of Operation," on page 19 Section 8.3, "I2C Master EEPROM 114. P0_MODE[2:0] P0_mode_strap[1:0] 000 ...

Page 60

... Section 7.1.1, "PHY Addressing," on page 60 DATASHEET Datasheet PIN(S) P1_MODE2 : P1_MODE1 : P1_MODE0 for P1_MODE1 Port 1 MII Basic P1_MODE0 Port 1 MII P1_MODE1 Port 1 MII Basic when in MII PHYADDR_LED5P Note 4.1 95. PHYADDR_LED5P MNGT1_LED4P : MNGT0_LED3P : E2PSIZE_LED2P : AMDIX2_LED1P : AMDIX1_LED0P Table 4.4 for details. SMSC LAN9303M/LAN9303Mi : ...

Page 61

... Section 5.2.2, "Ethernet PHY Interrupts," on page Power-Down," on page 108 power-down mode. Note: The Port 1 PHY is set into general power-down mode when Port 1 is configured to MII PHY, RMII PHY, or MII MAC mode. SMSC LAN9303M/LAN9303Mi Table 4.4 PIN/Shared Strap Mapping STRAP NAME 1 phy_addr_sel_strap mngt_mode_strap[1] ...

Page 62

... Interrupt Configuration Register and Interrupt Enable Register (INT_EN) is responsible for enabling/disabling the IRQ interrupt Interrupt Configuration Register (IRQ_CFG). A setting of all zeros disables the 62 DATASHEET Datasheet Interrupt Status Register (IRQ_CFG). aggregate and Interrupt Status Register Figure 5.1) Interrupt Status Interrupt De-assertion Interval SMSC LAN9303M/LAN9303Mi ...

Page 63

... GPIO bit of INT_STS register Figure 5.1 Functional Interrupt Register Hierarchy The following sections detail each category of interrupts and their related registers. Refer to Chapter 13, "Register Descriptions," on page 146 SMSC LAN9303M/LAN9303Mi Switch Fabric Interrupt Registers SW_IMR SW_IPR Buffer Manager Interrupt Registers BM bit ...

Page 64

... Buffer Manager, Switch Engine Port x MAC Interrupt Mask Switch Global bit of the Interrupt Enable Register bit of the Interrupt Configuration Section 6.6, "Switch Fabric Interrupts," Port 1 PHY bits of the Interrupt Status Port x PHY Port x PHY Interrupt Mask SMSC LAN9303M/LAN9303Mi Switch ...

Page 65

... Interrupt Status Register (INT_STS) In order for a device ready interrupt event to trigger the external IRQ interrupt pin, the Enable (READY_EN) be enabled via the IRQ Enable (IRQ_EN) SMSC LAN9303M/LAN9303Mi Port 1 PHY Interrupt Event (PHY_INT1) Interrupt Enable Register (INT_EN) bit of the Interrupt Configuration Register ...

Page 66

... Switch 162. These registers provide Switch Fabric manual flow (SWITCH_CSR_CMD), or the set of (SWITCH_CSR_DIRECT_DATA). The indirectly accessible Switch Fabric CSRs 226. 146. 66 DATASHEET Datasheet and Switch Fabric Switch Fabric CSR Interface Section 13.4, "Switch Fabric Control and Chapter 13, "Register SMSC LAN9303M/LAN9303Mi ...

Page 67

... Table 13.4, “Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map,” on page 174. Figure 6.1 illustrates the process required to perform a Switch Fabric CSR write. SMSC LAN9303M/LAN9303Mi (SWITCH_CSR_DATA). The write cycle is initiated with the CSR Busy (CSR_BUSY) bit set, the Read/Write (R_nW) ...

Page 68

... Read Command Register CSR_BUSY = 1 with the field set to the desired register and Auto Decrement CSR Busy (CSR_BUSY) Switch for reading sequential register or Auto Decrement field written with the desired register Switch Fabric CSR Switch is incremented or decremented Auto Increment SMSC LAN9303M/LAN9303Mi bit ...

Page 69

... TX_FC_x and RX_FC_x bits of the port’s manual flow control register. When Auto-negotiation is enabled and the MANUAL_FC_x bit is cleared, the switch port flow control enables during full-duplex are determined by Auto-negotiation. SMSC LAN9303M/LAN9303Mi CSR Read Auto Increment / ...

Page 70

... For the Virtual PHY, these and Virtual PHY Auto-Negotiation Link Partner (VPHY_AN_LP_BASE_ABILITY). Refer to for more information. 70 DATASHEET Datasheet and Section 7.3.1.3, "Virtual PHY BP_EN_x BP_EN_x X X RX_FC_x TX_FC_x X X RX_FC_x TX_FC_x BP_EN_x BP_EN_x Port x PHY Auto-Negotiation Virtual PHY Auto-Negotiation Section 7.3.1, SMSC LAN9303M/LAN9303Mi ...

Page 71

... Flow Control packet will be loaded into the pause counter. The pause function is enabled by either Auto-negotiation, or manually as discussed in "Flow Control Enable Logic," on page to the Switch Engine. Non-pause control frames are optionally filtered or forwarded. SMSC LAN9303M/LAN9303Mi 69. Pause frames are consumed by the MAC and are not sent 71 DATASHEET Section 6 ...

Page 72

... DATASHEET Datasheet RX Enable bit of the Table 13.14, “Indirectly and Section 13.4.2.3 through 244) 245) 246) 247) 248) 249) 252) 259) 260) 261) SMSC LAN9303M/LAN9303Mi Port ...

Page 73

... Total packets 512 through 1023 bytes in size Total packets 1024 through maximum bytes in size Total undersized packets Total bytes transmitted from all packets Total broadcast packets SMSC LAN9303M/LAN9303Mi Port x MAC Transmit Configuration Register (MAC_TX_CFG_x). (Section 13.4.2.25, on page 265) (Section 13.4.2.26, on page ...

Page 74

... Switch Engine ALR Write Data 0 Register and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1 Priority Priority Enable Figure 6.3 ALR Table Entry Structure 74 DATASHEET Datasheet 278) 279) 280) 281) Figure 6.3 displays for ... Port MAC Address SMSC LAN9303M/LAN9303Mi ...

Page 75

... Switch Engine ALR Command Status Register Engine ALR Write Data 0 Register Register (SWE_ALR_WR_DAT_1). SMSC LAN9303M/LAN9303Mi (SWE_PORT_INGRSS_CFG). Section 6.4.5, "Spanning Tree Support," on page and per entry with the Priority Enable bit, the transmit priority for MAC Switch Engine ALR Command Register ...

Page 76

... Switch Switch Engine ALR Read Data 1 with 0002h (Get First Entry). with 0000h (Clear the Get Switch Engine ALR Read Data with 0001h (Get Next Entry). with 0000h (Clear the Get for detailed SMSC LAN9303M/LAN9303Mi ...

Page 77

... ALR table with the ALR result indicating multiple destination ports and the VLAN broadcast domain containment resulted in zero valid destination ports, the packet is filtered. SMSC LAN9303M/LAN9303Mi is in effect). for additional information effect). (This rule is for a destination MAC address ...

Page 78

... Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 3b priority 3b calculation static DA override 3b DA Highest Priority ALR Priority Enable Bit 78 DATASHEET Datasheet Figure 6.4, the priority may programmable 2b Traffic Class priority queue table SMSC LAN9303M/LAN9303Mi ...

Page 79

... The transmit queue priority is based on the packet type and device configuration as shown in Figure 6.5 . Refer to (SWE_GLOBAL_INGRSS_CFG)," on page 303 Resolved Priority = Resolved Priority = ALR Priority IP Precedence Figure 6.5 Switch Engine Transmit Queue Calculation SMSC LAN9303M/LAN9303Mi Section 13.4.3.16, "Switch Engine Global Ingress Configuration Register for definitions of the configuration bits. Y Packet is IPv4 Use Precedence ...

Page 80

... Refer to through Section 13.4.3.35, on page 324 80 DATASHEET Datasheet Switch Engine VLAN Command Register (SWE_VLAN_WR_DATA), Switch Switch Engine VLAN Command through Section through Section Switch Engine Port 0 Ingress VLAN Switch Engine Port 1 Ingress Switch Engine Port for detailed descriptions of SMSC LAN9303M/LAN9303Mi ...

Page 81

... Port 0, which is connected to the host CPU, should normally be left in forwarding mode. Port State Hardware Action 11 - Disabled Received packets on the port are always discarded. Transmissions to the port are always blocked. Learning on the port is disabled. SMSC LAN9303M/LAN9303Mi Un-tag Member Un-tag Port 1 MII MII Figure 6 ...

Page 82

... The host CPU may send packets to the port in this state. Ingress Rate Enable (SWE_INGRSS_RATE_CFG). Once enabled, each incoming Rate Mode (SWE_INGRSS_RATE_CFG). Each stream can have a different CIR (SWE_INGRSS_RATE_WR_DATA). 82 DATASHEET Datasheet Software Action bit in the Switch Engine bits in the Switch Engine Ingress and Switch Engine SMSC LAN9303M/LAN9303Mi ...

Page 83

... CBS and EBS parameters, the token buckets will need to be normally depleted below these values before the values have any affect on limiting the maximum value of the token buckets. Refer to Section 13.4.3.25, on page 313 descriptions. SMSC LAN9303M/LAN9303Mi Table 6.3 Typical Ingress Rate Settings 80 nS 100 nS 120 nS 140 nS ...

Page 84

... Figure 6.7 Switch Engine Ingress Flow Priority Selection Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII Use IP 3b Priority 3b 3b Calculation Port Default Table DA Highest Priority ALR Priority Enable Bit Priority 84 DATASHEET Datasheet 3b Static DA flow priority Override SMSC LAN9303M/LAN9303Mi ...

Page 85

... The ingress flow calculation is based on the packet type and the device configuration as shown in Figure 6.8. Y Use Precedence Flow Priority = Flow Priority = ALR Priority IP Precedence Figure 6.8 Switch Engine Ingress Flow Priority Calculation SMSC LAN9303M/LAN9303Mi wait for ALR result Packet is IPv4 N N Flow Priority = ...

Page 86

... Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL) Switch Engine Global Ingress Configuration 75. The host software should also forward the original Switch Engine Global Ingress Configuration Register 86 DATASHEET Datasheet Bandwidth 75 Mbps 50 Mbps 40 Mbps 20 Mbps 10 Mbps 5 Mbps 2.4 Mbps 1.2 Mbps 900 Kbps 600 Kbps 300 Kbps SMSC LAN9303M/LAN9303Mi ...

Page 87

... If VID bit 3 is one, then the normal ALR lookup is performed and learning is performed on the source (SWE_PORT_INGRSS_CFG) The STP port state override is taken from the ALR entry. SMSC LAN9303M/LAN9303Mi Switch Engine Port Mirroring Register are used to enable a special VLAN tag that and the port state for the CPU port is set to Forwarding or Learning). ...

Page 88

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII is followed with the exception that the special tag is skipped Jumbo2K of Port 0 should be set. 88 DATASHEET Datasheet is followed with the exception that Section bit in the Port x MAC Receive configures the switch to SMSC LAN9303M/LAN9303Mi ...

Page 89

... Yellow bit in the Buffer Manager Configuration Register (BM_CFG) randomly discarded based on the moving average number of buffers used by the ingress port. SMSC LAN9303M/LAN9303Mi Buffer Manager Drop Level Register Buffer Manager Broadcast Buffer Level Register Section 6.4.6, "Ingress Flow Metering and Coloring," ...

Page 90

... Transmit Priority Queue Section 13.4.4.14 through Section 13.4.4.19 90 DATASHEET Datasheet Buffer Buffer Buffer Fixed Priority Queue Servicing Fixed Priority Queue is cleared, a weighted round- Servicing, such that a lower for detailed register SMSC LAN9303M/LAN9303Mi ...

Page 91

... CPU Port - Packets transmitted from this port type generally contain a special tag. Special tags are described in detail in Hybrid Port - Generally, this port type supports a mix of normal-tagged and non-tagged packets the most complex, but most flexible port type. SMSC LAN9303M/LAN9303Mi Table 6.5 Typical Egress Rate Settings BANDWIDTH @ BANDWIDTH @ ...

Page 92

... Priority field of the new VLAN tag Buffer Manager Egress Port Type Register for the egress port is clear, the packet passes untouched. for the egress port are clear, the packet passes 92 DATASHEET Datasheet Section 6.4.4, "VLAN Buffer Manager Buffer Manager Egress Port SMSC LAN9303M/LAN9303Mi ...

Page 93

... The default VLAN ID and priority of each port may be configured via the following registers: Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_0) Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) SMSC LAN9303M/LAN9303Mi Figure 6.9. Receive Tag ...

Page 94

... The Switch Fabric is capable of generating multiple maskable interrupts from the Buffer Manager, Switch Engine, and MACs. These interrupts are detailed in on page 64. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII Section 5.2.1, "Switch Fabric Interrupts," 94 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

Page 95

... Table 7.1 Default PHY Serial MII Addressing VIRTUAL PHY DEFAULT phy_addr_sel_strap ADDRESS VALUE 0 1 SMSC LAN9303M/LAN9303Mi Section 13.3, "Ethernet PHY Control and Status Registers" Table 7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can PHY Address (PHYADD) field in the PORT 1 PHY DEFAULT ...

Page 96

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII and 100BASE-TX Receive and 10BASE-T Receive 10/100 Transmitter HP Auto-MDIX 10/100 Reciever LEDs PLL To GPIO/LED From Controller System Clocks Controller Figure 7.1 Port x PHY Block Diagram 96 DATASHEET Datasheet Figure 7.1. TXPx/TXNx To External RXPx/RXNx Port x Ethernet Pins SMSC LAN9303M/LAN9303Mi ...

Page 97

... IDLE code-group is /I/, a transmit error code-group is /H/, etc. CODE GROUP SYM 11110 0 0 01001 1 1 10100 2 2 SMSC LAN9303M/LAN9303Mi Figure 7.2. Shaded blocks are those which are 100M PLL MII MAC 4B/5B 25MHz Interface by 4 bits Encoder 125 Mbps Serial 100M ...

Page 98

... Sent for rising MII Transmitter Enable signal (TXEN) Sent for falling MII Transmitter Enable signal (TXEN) Sent for falling MII Transmitter Enable signal (TXEN) Sent for rising MII Transmit Error (TXER) INVALID INVALID INVALID INVALID INVALID INVALID SMSC LAN9303M/LAN9303Mi ...

Page 99

... Phase Lock Loop (PLL) The 100M PLL locks onto the reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE-TX Transmitter. SMSC LAN9303M/LAN9303Mi Table 7.2 4B/5B Code Table (continued) RECEIVER INTERPRETATION 99 ...

Page 100

... Shaded blocks are those which are internal 100M PLL MII MAC 25MHz 4B/5B Interface by 4 bits Decoder 125 Mbps Serial MLT-3 recovery, Equalizer MLT-3 and BLW Correction RJ45 MLT-3 MLT-3 6 bit Data 100 DATASHEET Datasheet Descrambler 25MHz by 5 bits and SIPO DSP: Timing CAT-5 SMSC LAN9303M/LAN9303Mi ...

Page 101

... MII to the Switch Fabric MAC. The MII MAC Interface is described in detail in Interface". Note: The PHY is connected to the Switch Fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details. SMSC LAN9303M/LAN9303Mi 101 DATASHEET Section 7.2.7, "MII MAC Revision 1.4 (07-07-10) ...

Page 102

... RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition is indicated by the 10Base-T Polarity State (XPOL) Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII Section 7.2.7, "MII MAC in the Port x PHY Special Control/Status Indication 102 DATASHEET Datasheet Interface". SMSC LAN9303M/LAN9303Mi ...

Page 103

... Auto-negotiation (digital) 100M ADC (analog) 100M PLL (analog) 100M equalizer/BLW/clock recovery (DSP) 10M SQUELCH (analog) 10M PLL (analog) 10M TX Driver (analog) SMSC LAN9303M/LAN9303Mi Auto-Negotiation (PHY_AN) (PHY_BASIC_CONTROL_x). Port x PHY Auto-Negotiation Advertisement Section 13.3.2.5, "Port x PHY Auto-Negotiation 212. Refer to Port x PHY Special Control/Status Port x PHY Auto-Negotiation Link (PHY_AN_LP_BASE_ABILITY_x) ...

Page 104

... DATASHEET Datasheet Reset (PHY_RST) bit of the 107) Restart Auto- Reset Control Register (RESET_CTL)) Port x PHY 100BASE-X Half Duplex, and 100BASE-X allows Port x PHY Auto-Negotiation Restart Auto-Negotiation (PHY_RST_AN) Port x PHY Basic Control Register Symmetric Pause SMSC LAN9303M/LAN9303Mi 120) Port ...

Page 105

... Parallel Detection If LAN9303M/LAN9303Mi is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard. This ability is known as “ ...

Page 106

... Note 7.1 on page 96 ( bit of the for Port 1 and Port 2, respectively). (manual_mdix_strap_1 Auto-MDIX Control (AMDIXCTRL) Section 3.2, "Pin Descriptions," on bits of the Port x PHY signaling 1 TXPx 2 TXNx RXPx 3 Not Used 4 Not Used 5 RXNx 6 Not Used 7 Not Used 8 Cross-Over Cable SMSC LAN9303M/LAN9303Mi , ) Port and ...

Page 107

... The SMI interface consists of the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals interface to the MDIO and MDC pins of LAN9303M/LAN9303Mi (or the PMI block in I PHY registers. Refer to supported registers and register descriptions. Non-supported registers will be read as FFFFh. ...

Page 108

... Port 2 PHY is reset by setting the Reset (PHY_RST) for additional information. 108 DATASHEET Datasheet bit of the Port x PHY bit of Energy Port x PHY Mode Control/Status 48. does not Port 2 PHY bit of the Port x PHY Basic Control Section 7.2.9, "PHY SMSC LAN9303M/LAN9303Mi ...

Page 109

... The auto-negotiation result (speed, duplex, and pause) is determined and registered. The auto-negotiation result (speed and duplex) is determined using the Highest Common Denominator (HCD) of the Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) SMSC LAN9303M/LAN9303Mi Auto-Negotiation (VPHY_AN) and is restarted by the occurrence of any of the following Virtual PHY Reset (VPHY_RST) ...

Page 110

... Section 13.2.6.6, "Virtual PHY inputs are considered to be static. Link Partner Auto-Negotiation Able is set, and the technology Virtual PHY will be set, Auto-Negotiation (VPHY_AN) bit) and duplex (VPHY_BASIC_CTRL). should be SMSC LAN9303M/LAN9303Mi as bit of Link bit ...

Page 111

... Virtual PHY Software Reset via RESET_CTL The Virtual PHY can be reset via the Reset (VPHY_RST) bit. This bit is self clearing after approximately 102uS. SMSC LAN9303M/LAN9303Mi Symmetric Pause (VPHY_AN_ADV). This allows the Virtual Table 13.6, “Emulated Link Partner Pause Flow Control 189. ...

Page 112

... This bit is self clearing and will return to 0 after the reset is complete. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII Reset (VPHY_RST) 112 DATASHEET Datasheet bit of the Virtual PHY Basic SMSC LAN9303M/LAN9303Mi ...

Page 113

... Typically the receiver acknowledges each byte. If the master is the receiver, it does not generate an acknowledge on the last byte of a transfer. This informs the slave to not drive the next byte of data so that the master may generate a stop or repeated start condition. SMSC LAN9303M/LAN9303Mi 2 C slave controller. ...

Page 114

... Data Valid Stop Condition or Ack 2 C EEPROM controller EEPROMs are supported. The EEPROM Controller Address (E2P_CMD). Within each size range, the 2 C operation are shown in Table 8.1. EEPROM TYPES 24xx00, 24xx01, 24xx02, 24xx04, 24xx08, 24xx16 24xx32, 24xx64, 24xx128, 24xx256, 24xx512 SMSC LAN9303M/LAN9303Mi ...

Page 115

... K Chip / Block R/~W Select Bits Single Byte Addressing Read For a register level description of a read operation, refer to Controller Operation," on page SMSC LAN9303M/LAN9303Mi EEPROM Controller Timeout (EPC_TIMEOUT) is set EEPROM addressing bit order for single and double byte addressing. Control Byte A A ...

Page 116

... C master will issue a stop and repeat the poll. If the acknowledge does not 116 DATASHEET Datasheet EEPROM Command Register 2 C master Data Byte ... Data Byte ... Section 8.4, "EEPROM Loader" Section 8.3.7, "I2C Master EEPROM EEPROM Controller Timeout is set. SMSC LAN9303M/LAN9303Mi for ...

Page 117

... The first master to reach its high time will once again drive the clock low. The fastest master therefore determines the actual high time. The process then repeats. Clock synchronization is similar to the cycle stretching that can be done by a slave device, with the SMSC LAN9303M/LAN9303Mi 2 C EEPROM byte write. ...

Page 118

... The EEPROM Controller Busy (EPC_BUSY) is set. The completion of the operation is indicated when the bit is cleared. 118 DATASHEET Datasheet 2 C EEPROM Command Register Loader") Section 8.2, EEPROM Data EEPROM Controller to the desired field bit of the EEPROM SMSC LAN9303M/LAN9303Mi ...

Page 119

... EEPROM read or write operation. EEPROM Write E2P_DATA EPC_BUSY = 0 Figure 8.6 EEPROM Access Flow Diagram SMSC LAN9303M/LAN9303Mi EEPROM Controller Command (EPC_COMMAND) fields of the EEPROM Controller Busy (EPC_BUSY) (E2P_CMD). The completion of the operation is indicated when the bit is cleared, at which time the data from the EEPROM may (E2P_DATA) ...

Page 120

... Byte on the Network th 5 Byte on the Network th 6 Byte on the Network A5h See Table 8.3 A5h See Section 8.4.5, "Register Data" See Section 8.4.5, "Register Data" (Digital Reset (DIGITAL_RST) bit in the bit in the Device is cleared and no writes to the Figure 8.7. SMSC LAN9303M/LAN9303Mi ...

Page 121

... Update VPHY registers Update registers: P1_MII_BASIC_CONTROL, LED_CFG, MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_0 Read Byte 12 Byte 12 = A5h Do register data loop Figure 8.7 EEPROM Loader Flow Diagram SMSC LAN9303M/LAN9303Mi Load PHY registers with N current straps Load PHY registers with N current straps N Y 121 DATASHEET EPC_BUSY = 0 Revision 1 ...

Page 122

... SQE_test_ strap_1 disable_strap _1 speed_ duplex_ autoneg_ strap_2 strap_2 strap_2 speed_ duplex_pol_ SQE_test_ strap_0 strap_0 disable_strap _0 Port x PHY Auto- Port x PHY Special Modes Register is written with the new is written with the new defaults SMSC LAN9303M/LAN9303Mi are ...

Page 123

... EEPROM space). This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a value of A5h, the data that follows is recognized as a sequence of bursts. Otherwise, the EEPROM SMSC LAN9303M/LAN9303Mi Restart Auto-Negotiation (PHY_RST_AN) register to determine the new Auto-negotiation results. ...

Page 124

... MII Busy (MIIBZY) are cleared before performing any register eeprom_size_strap bit of the EEPROM Command Register (E2P_CMD) 124 DATASHEET Datasheet bit bit of the Switch Fabric CSR bit of the PHY bit in the EEPROM Command which specifies a range EEPROM will be cleared. 365. SMSC LAN9303M/LAN9303Mi ...

Page 125

... Control Byte SMSC LAN9303M/LAN9303Mi Section 8.4.4.2, respectively managed mode, the I C slave interface is used for CPU management of the configuration straps are set to 10b, respectively. The slave serial interface (start and stop condition detection, data bit 2 C-Bus Specification for detailed I Figure 8 ...

Page 126

... Once the correct pattern is can be polled to determine when the device initialization Section 4.2, "Resets," on page 48 for additional information. 126 DATASHEET Datasheet 2 C reads from unused register addresses Data Byte... ...Data Byte .. . Data m+1 Byte... ...Data n Byte .. . Device Ready (READY) bit in the SMSC LAN9303M/LAN9303Mi ...

Page 127

... Control Byte Control Byte Address Byte SMSC LAN9303M/LAN9303Mi Section 8.5.1, a register is written to the device when C writes must not be performed to unused register addresses. Address Byte Data Byte Single Register Write Data 1 Byte ...Data m Byte .. . .. . ...

Page 128

... SQEOFF (VPHY_SPECIAL_CONTROL_STATUS). 128 DATASHEET Datasheet Isolate (VPHY_ISO) bit of is set, MII data path output pins are Isolate (VPHY_ISO) bit Turbo MII Enable bit of the Virtual Speed Select LSB is set. bit of the Virtual PHY Special bit of the Virtual PHY Special SMSC LAN9303M/LAN9303Mi ...

Page 129

... The 50MHz RMII reference clock can be selected from either the P0_OUTCLK pin input or the internal 50MHz clock. The choice is based on the setting of the Special Control/Status Register SMSC LAN9303M/LAN9303Mi Collision Test (VPHY_COL_TEST) is set. In this test mode, any transmissions from Switch Collision Test Port 0 Loopback (VPHY_LOOPBACK) is set ...

Page 130

... DATASHEET Datasheet bit of the Virtual PHY SQEOFF bit has no Collision has no Switch Collision Test Port 0 bit of is set. In this bit of the Virtual PHY bit of the Virtual PHY Special is set. Transmissions from the Switch bit is set. Switch Engine bit. SMSC LAN9303M/LAN9303Mi ...

Page 131

... External MAC loopback is enabled when the (P1_MII_BASIC_CONTROL) Engine and are not used for purposes of signaling data valid, collision or carrier sense to the Switch SMSC LAN9303M/LAN9303Mi is set, MII data path output pins are three-stated, (P1_MII_BASIC_CONTROL). When set, this bit changes the data rate of ...

Page 132

... MII management RMII Clock Direction RMII Clock Direction 132 DATASHEET Datasheet Collision Test bit of the Port 1 MII Basic Isolate bit. bit of the Port 1 MII Basic bit of the Port 1 MII Basic SQEOFF bit has no effect when operating in Collision has no effect on system SMSC LAN9303M/LAN9303Mi ...

Page 133

... MAC are ignored. An internal collision signal to the Switch Engine is available and is asserted when the Switch Collision Test Port 1 of the setting of the Isolate SMSC LAN9303M/LAN9303Mi Loopback bit of the is set. Transmissions from the external MAC are not sent to the Switch Switch Looopback Port 1 is set ...

Page 134

... Multiplexer. The SMI Slave inputs are set to 01b. A list of Section 2.3, "Modes of Table 10.1. The device Table 10.1. All addresses and data are TURN- AROUND TIME Note 10.2 DATA Z0 DDDDDDDDDDDDDDDD 1111110000000000 5432109876543210 10 DDDDDDDDDDDDDDDD 1111110000000000 5432109876543210 SMSC LAN9303M/LAN9303Mi Datasheet SMI IDLE Note 10 ...

Page 135

... Note: In the event that a reset condition terminates between halves of 16-bit read pair, the device will not expect another 16-bit read to complete the DWORD cycle. Only specific registers may be read during a reset. Refer to SMSC LAN9303M/LAN9303Mi should be polled. Once the correct pattern is can be polled to determine when the device initialization Section 4.2, " ...

Page 136

... Register Data burst sequence Section 8.4, "EEPROM Loader," on page 120 136 DATASHEET Datasheet Table 10.2. All addresses and data are TURN- TIME DATA Z0 DDDDDDDDDDDDDDDD 10 DDDDDDDDDDDDDDDD PHY Management for detailed information on these registers. and PHY Management for additional SMSC LAN9303M/LAN9303Mi IDLE Note 10 Section ...

Page 137

... MDCLK PHY1 MDI MDO MDIO_ DIR MDCLK Management Mode Selection Figure 10.1 MII Mux Management Path Connections - MAC Mode SMI Managed SMSC LAN9303M/LAN9303Mi and Section 8.4, "EEPROM Loader," on page 120 Management Mode Selection MDO MDCLK MDI MDO_EnN PMI Parallel Slave ...

Page 138

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 2 C Managed 2 C slave interface or the EEPROM Loader. for additional information. Management Mode Selection MDO MDCLK PMI Parallel Slave 138 DATASHEET Datasheet MII Pins MDIO_DIR MDO MDIO MDI MDC_DIR MDC_ OUT MDC MDC_IN MDI MDO_EnN 2 C Managed SMSC LAN9303M/LAN9303Mi ...

Page 139

... MDCLK PHY1 MDI MDO MDIO_ DIR MDCLK Management Mode Selection Figure 10.3 MII Mux Management Path Connections - PHY Mode SMI Managed SMSC LAN9303M/LAN9303Mi and Section 8.4, "EEPROM Loader," on page 120 Management Mode Selection MDO MDCLK MDI MDO_EnN PMI Parallel Slave ...

Page 140

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 2 C Managed Management Mode Selection MDO MDCLK PMI Parallel Slave 140 DATASHEET Datasheet 2 C slave interface or the EEPROM for additional information. MII Pins MDIO_DIR MDO MDIO MDI MDC_DIR MDC_ OUT MDC MDC_IN MDI MDO_EnN 2 C Managed SMSC LAN9303M/LAN9303Mi ...

Page 141

... When the maximum count has been reached, the counter rolls over to zeros. The FRC does not generate interrupts. Note: The free running counter can take up to 160nS to clear after a reset event. SMSC LAN9303M/LAN9303Mi field of the General Purpose Timer Configuration Register General Purpose Timer Enable (TIMER_EN) is asserted (1) ...

Page 142

... General Purpose I/O Configuration (GPIO_DATA_DIR). The GPIO Direction 5- (GPIO_DATA_DIR). When GPIO Buffer Type 5- (GPIO_CFG). Push/pull and bit in the General GPIO Data 5-0 (GPIOD[5:0]) General Purpose I/O Interrupt GPIO Interrupt[5:0] (GPIO[5:0]_INT) bit. The Chapter 5, "System Interrupts," on SMSC LAN9303M/LAN9303Mi ...

Page 143

... Port 1 internal PHY enabled) Activity Port 1 (if Port 1 internal PHY disabled) SMSC LAN9303M/LAN9303Mi bits in the General Purpose I/O Configuration Register (GPIO_INT_STS_EN). When cleared, a low logic level on the LED Enable 5-0 (LED_EN[5:0]) (LED_CFG). These bits allow the configuration of each LED pin ...

Page 144

... LED polarity hard-straps. LED polarity is determined by these hard-straps as is 00b, 01b, or 10b, the following LED function definitions 144 DATASHEET Datasheet 10b 11b TX_EN Port 1 Port 1 enabled) TX Port 1 disabled) Speed RX_DV Port 1 Port 1 enabled) RX Port 1 disabled) are described in the following sections. 51. The LED polarity cannot be modified SMSC LAN9303M/LAN9303Mi ...

Page 145

... Note: Link indication does not affect this function. RX_DV Port 2 - Non-stretched RX_DV signal from the PHY to the Switch Fabric. Note: Link indication does not affect this function. SMSC LAN9303M/LAN9303Mi is 11b, the following LED rules apply: led_pol_strap[5:0] LED polarity hard-straps. The LED ...

Page 146

... Switch CSR Direct Data ... Registers 200h 1DCh Virtual PHY Registers 1C0h 1B0h Switch Interface Registers 1ACh 19Ch RESERVED 0ACh PHY Management Interface 0A8h 0A4h Registers 050h 04Ch RESERVED Base + 000h Figure 13.1 Base Register Memory Map 146 DATASHEET Datasheet SMSC LAN9303M/LAN9303Mi ...

Page 147

... Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN9303M/LAN9303Mi Table 13.1 Register Bit Types REGISTER BIT DESCRIPTION ...

Page 148

... PHY Management Interface Data Register, Section 13.2.5.1 PHY Management Interface Access Register, Section 13.2.5.2 Reserved for Future Use 148 DATASHEET Datasheet 2 C serial interface or the MIIM/SMI Section 13.2.7.1 Section 13.2.1.1 Section 13.2.1.2 Section 13.2.1.3 Section 13.2.7.2 Section 13.2.7.3 Section 13.2.7.5 Section 13.2.7.6 SMSC LAN9303M/LAN9303Mi ...

Page 149

... RESET_CTL 1FCh RESERVED 200h-2DCh SWITCH_CSR_DIRECT_DATA 2E0h-3FFh RESERVED SMSC LAN9303M/LAN9303Mi REGISTER NAME Port 1 Manual Flow Control Register, Port 2 Manual Flow Control Register, Port 0 Manual Flow Control Register, Switch Fabric CSR Interface Data Register, Section 13.2.4.4 Switch Fabric CSR Interface Command Register, Section 13 ...

Page 150

... Disable output on IRQ pin 1: Enable output on IRQ pin 7:5 RESERVED Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 62. 054h Size: DESCRIPTION 150 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00h SMSC LAN9303M/LAN9303Mi ...

Page 151

... When configured as an open-drain output, the IRQ_POL bit is ignored and the interrupt output is always active low. 0: IRQ pin open-drain output 1: IRQ pin push-pull driver Note 13.1 Register bits designated as NASR are not reset when the in the Reset Control Register (RESET_CTL) SMSC LAN9303M/LAN9303Mi DESCRIPTION is set. 151 DATASHEET TYPE DEFAULT ...

Page 152

... Software Interrupt Enable Interrupt Enable Register (INT_EN) Switch Global Interrupt Pending Register Port x PHY Interrupt Source Port x PHY Interrupt Source General Purpose Timer Count Register General Purpose 152 DATASHEET Datasheet 32 bits Interrupt Enable Register (INT_EN). Where TYPE DEFAULT R/ set high SMSC LAN9303M/LAN9303Mi ...

Page 153

... Port 1 PHY Interrupt Event Enable (PHY_INT1_EN) 25:20 RESERVED 19 GP Timer Interrupt Enable (GPT_INT_EN) 18:13 RESERVED 12 GPIO Interrupt Event Enable (GPIO_EN) 11:0 RESERVED SMSC LAN9303M/LAN9303Mi 05Ch Size: Interrupt Status Register (INT_STS) Software Interrupt Enable Interrupt Status Register (INT_STS) DESCRIPTION 153 DATASHEET 32 bits register (SW_INT_EN)) ...

Page 154

... Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1E0h Size: DESCRIPTION General Purpose (GPIO_INT_STS_EN). 154 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 0h SMSC LAN9303M/LAN9303Mi ...

Page 155

... If the pin is an input, the data reflects the current state of the corresponding GPIO pin. If the pin is an output, the data is the value that was last written into this register. The pin direction is determined by the GPDIR bits of this register. SMSC LAN9303M/LAN9303Mi 1E4h Size: DESCRIPTION ...

Page 156

... DESCRIPTION GPIO Interrupt bit of the Interrupt Enable Register General Purpose I/O Configuration 156 DATASHEET Datasheet 32 bits bit of the Interrupt Status Register bit of the TYPE DEFAULT R/WC 0h SMSC LAN9303M/LAN9303Mi ...

Page 157

... Note 13.3 The default value of this field is determined by the configuration strap LED_en_strap[5:0]. Configuration strap values are latched on power-on reset or nRST de-assertion. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 51 SMSC LAN9303M/LAN9303Mi 1BCh Size: DESCRIPTION 143 ...

Page 158

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII for additional information. 1B4h Size: DESCRIPTION (E2P_DATA). The E2P_CMD and EEPROM Controller Timeout for more information. 158 DATASHEET Datasheet Section 8.3, "I2C Master EEPROM 32 bits TYPE DEFAULT R SMSC LAN9303M/LAN9303Mi ...

Page 159

... The bit is also set if the EEPROM fails to respond with the appropriate ACKs, if the EEPROM slave device holds the clock low for more than 30mS the I C bus is not acquired within 1.92 seconds unsupported EPC_COMMAND is attempted. This bit is cleared when written high. SMSC LAN9303M/LAN9303Mi DESCRIPTION [28] Operation 0 READ 1 ...

Page 160

... This field is used by the EEPROM Controller to address a specific memory location in the serial EEPROM. This address must be byte aligned. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII DESCRIPTION Digital Reset (DIGITAL_RST) resets, or 160 DATASHEET Datasheet TYPE DEFAULT RO 0b R/W 0000h SMSC LAN9303M/LAN9303Mi ...

Page 161

... This read/write register is used in conjunction with the perform read and write operations with the serial EEPROM. BITS 31:8 RESERVED 7:0 EEPROM Data (EEPROM_DATA) This field contains the data read from or written to the EEPROM. SMSC LAN9303M/LAN9303Mi 1B8h Size: EEPROM Command Register (E2P_CMD) DESCRIPTION 161 DATASHEET 32 bits ...

Page 162

... Size: Section 6.2.3, "Flow Control Enable Logic," on page 69 DESCRIPTION 162 DATASHEET Datasheet Table 13.14. 66. For detailed 32 bits for additional Section 13.3.2.5, on page 212) TYPE DEFAULT RO - R/W Note 13.4 RO Note 13.5 RO Note 13.5 RO Note 13.5 R/W Note 13.6 SMSC LAN9303M/LAN9303Mi ...

Page 163

... The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values. See information. SMSC LAN9303M/LAN9303Mi DESCRIPTION BP_EN_strap_1 for additional information. FD_FC_strap_1 Section 4.2.4, " ...

Page 164

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1A4h Size: Section 6.2.3, "Flow Control Enable Logic," on page 69 DESCRIPTION 164 DATASHEET Datasheet 32 bits for additional Section 13.3.2.5, on page 212) TYPE DEFAULT RO - R/W Note 13.9 RO Note 13.10 RO Note 13.10 RO Note 13.10 R/W Note 13.11 R/W Note 13.11 SMSC LAN9303M/LAN9303Mi ...

Page 165

... Note 13.12 The default value of this field is determined by the The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values. See SMSC LAN9303M/LAN9303Mi DESCRIPTION for additional information. Section 4.2.4, "Configuration Straps," on page 51 ...

Page 166

... Section 6.2.3, "Flow Control Enable Logic," on page 69 Section 13.2.6.5, "Virtual PHY Auto-Negotiation Advertisement are not affected by the values of this register. DESCRIPTION 166 DATASHEET Datasheet 32 bits for additional TYPE DEFAULT RO - R/W Note 13.13 RO Note 13.14 RO Note 13.14 RO Note 13.14 R/W Note 13.15 R/W Note 13.15 SMSC LAN9303M/LAN9303Mi ...

Page 167

... EEPROM Loader re-writes the value, this register is updated with the new values. In MAC mode, this bit is not re-written by the EEPROM Loader and has a default value of “1”. See Section 4.2.4, "Configuration Straps," on page 51 SMSC LAN9303M/LAN9303Mi DESCRIPTION BP_EN_strap_0 for more information. ...

Page 168

... Switch Fabric CSR Interface Command Register to perform read and write operations with the Switch Fabric CSR’s. Refer to DESCRIPTION CSR Address (CSR_ADDR[15:0]) Read/Write (R_nW) (SWITCH_CSR_CMD). 168 DATASHEET Datasheet 32 bits for details on the registers TYPE DEFAULT R/W 00000000h bit in Read/Write SMSC LAN9303M/LAN9303Mi ...

Page 169

... SWITCH_CSR_DATA register. 0: Disable Auto Decrement 1: Enable Auto Decrement 27:20 RESERVED SMSC LAN9303M/LAN9303Mi 1B0h Size: Switch Fabric CSR Interface Data Register to control the read and write operations to the various Switch Fabric CSR’s. DESCRIPTION (SWITCH_CSR_DATA) ...

Page 170

... Accessible Switch Control and Status Registers,” on page 226 Switch Fabric CSR addresses. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII DESCRIPTION Table 13.14, “Indirectly for a list of 170 DATASHEET Datasheet TYPE DEFAULT R/W 0h R/W 00h SMSC LAN9303M/LAN9303Mi ...

Page 171

... MAC Address for Port 0. 15:0 Physical Address[47:32] This field contains the upper 16-bits (47:32) of the physical address of the Switch Fabric MACs. Bits 41 and 10 are ignored if SMSC LAN9303M/LAN9303Mi 1F0h Size DESCRIPTION DiffPauseAddr 171 ...

Page 172

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1F4h Size for information on using the EEPROM Loader. DESCRIPTION Register Location Written SWITCH_MAC_ADDRL[7:0] SWITCH_MAC_ADDRL[15:8] SWITCH_MAC_ADDRL[23:16] SWITCH_MAC_ADDRL[31:24] SWITCH_MAC_ADDRH[7:0] SWITCH_MAC_ADDRH[15:8] 172 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W FF0F8000h Order of Reception on Ethernet SMSC LAN9303M/LAN9303Mi ...

Page 173

... SWITCH_MAC_ADDRH 31 24 78h SWITCH_MAC_ADDRL Figure 13.2 Example SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Setup Note: By convention, the right nibble of the left most byte of the Ethernet address (in this example, the 2 of the 12h) is the most significant nibble and is transmitted/received first. SMSC LAN9303M/LAN9303Mi BCh 9Ah ...

Page 174

... CSR CSR Busy (CSR_BUSY) bit is cleared. The address that is set is mapped via Section TYPE DEFAULT WO 00000000h Switch Fabric and Switch Fabric CSR Interface SWITCH_CSR_DIRECT_DATA ADDRESS 200h 204h 208h 20Ch 210h 214h 218h 21Ch 220h 224h SMSC LAN9303M/LAN9303Mi ...

Page 175

... SWE_GLB_INGRESS_CFG SWE_PORT_INGRESS_CFG SWE_ADMT_ONLY_VLAN SWE_PORT_STATE SWE_PRI_TO_QUE SWE_PORT_MIRROR SWE_INGRESS_PORT_TYP SWE_BCST_THROT SWE_ADMT_N_MEMBER SWE_INGRESS_RATE_CFG SWE_INGRESS_RATE_CMD SWE_INGRESS_RATE_WR_DATA SWE_INGRESS_REGEN_TBL_0 SWE_INGRESS_REGEN_TBL_1 SWE_INGRESS_REGEN_TBL_2 SWE_IMR BM_CFG SMSC LAN9303M/LAN9303Mi SWITCH FABRIC CSR REGISTER # Switch Port 2 CSRs 0C01h 0C40h 0C41h 0C80h Switch Engine CSRs 1800h 1801h 1802h 1809h 180Bh 180Ch 1811h 1812h ...

Page 176

... DATASHEET Datasheet SWITCH_CSR_DIRECT_DATA ADDRESS 29Ch 2A0h 2A4h 2A8h 2ACh 2B0h 2B4h 2B8h 2BCh 2C0h 2C4h 2C8h 2CCh 2D0h 2D4h 2D8h 2DCh SMSC LAN9303M/LAN9303Mi ...

Page 177

... Upon a read, the value returned depends on the (MIIWnR) bit in the (PMI_ACCESS). If PHY. If MII Write (MIIWnR) written into this register. SMSC LAN9303M/LAN9303Mi for additional information on the PHY registers. Refer 0A4h Size: PHY Management Interface Access Register DESCRIPTION MII Write PHY Management Interface Access Register ...

Page 178

... If this bit (PMI_DATA). PHY Management Interface or PHY Management Interface Access Register PHY Management Interface Data Register PHY Management Interface Data Register 178 DATASHEET Datasheet 32 bits PHY Management Interface Data TYPE DEFAULT RO - R/W 00000b R/W 00000b Section 13. R/W 0b PHY SMSC LAN9303M/LAN9303Mi ...

Page 179

... VPHY_ID_LSB 4 VPHY_AN_ADV 5 VPHY_AN_LP_BASE_ABILITY 6 VPHY_AN_EXP 31 VPHY_SPEC_CTRL_STATUS SMSC LAN9303M/LAN9303Mi Section 2.3, "Modes of Operation," on page 19 Table 13.5. For more information on the Virtual PHY access Section 13.3. For Virtual PHY functionality and operation information, see 109. REGISTER NAME Virtual PHY Basic Control Register, Virtual PHY Basic Status Register, ...

Page 180

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1C0h Size: 0 Section 8.4, "EEPROM Loader," on page 120 DESCRIPTION bit is disabled. and Duplex Mode (VPHY_DUPLEX) (Note 13.19) 180 DATASHEET Datasheet 32 bits for more TYPE DEFAULT R/W 0b R/W 0b Auto- R/W 1b Speed Select bits R/W 0b R SMSC LAN9303M/LAN9303Mi ...

Page 181

... Note 13.18 The reserved bits 31-16 are used to pad the register to 32-bits so that each register DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide. Note 13.19 The isolation does not apply to the MII management pins (MDIO). SMSC LAN9303M/LAN9303Mi DESCRIPTION Auto-Negotiation (VPHY_AN) 181 ...

Page 182

... No extended status information in Register 15 1: Extended status information in Register 15 7 RESERVED Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1C4h Size: 1 DESCRIPTION 182 DATASHEET Datasheet 32 bits TYPE DEFAULT Note 13. Note 13. Note 13. Note 13. SMSC LAN9303M/LAN9303Mi ...

Page 183

... Note 13.24 The Virtual PHY never has remote faults, its link is always up, and does not detect jabber. Note 13.25 The VIrtual PHY supports basic and some extended register capability. The Virtual PHY supports Registers 0-6 (per the IEEE 802.3 specification). SMSC LAN9303M/LAN9303Mi DESCRIPTION bit is first cleared on a reset, but set shortly after (when for additional details ...

Page 184

... Note 13.27 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1C8h Size: 2 Virtual PHY Identification LSB Register DESCRIPTION (Note 13.27). 184 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 0000h SMSC LAN9303M/LAN9303Mi ...

Page 185

... Note 13.28 The reserved bits 31-16 are used to pad the register to 32-bits so that each register DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide. Note 13.29 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier. SMSC LAN9303M/LAN9303Mi 1CCh Size: 3 ...

Page 186

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1D0h Size: 4 Section 8.4, "EEPROM Loader," on page 120 DESCRIPTION 186 DATASHEET Datasheet 32 bits for more TYPE DEFAULT Note 13. Note 13. R/W Note 13.33 R/W Note 13. Note 13.34 R/W 1b R/W 1b R/W 1b SMSC LAN9303M/LAN9303Mi ...

Page 187

... Configuration strap values are latched upon the de-assertion of a chip-level reset as described in Note 13.34 Virtual 100BASE-T4 is not supported. Note 13.35 The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this field. SMSC LAN9303M/LAN9303Mi DESCRIPTION bit is not useful since there is no actual link partner to send a fault to. and Asymmetric Pause bits default the strap is high (neither Symmetric and Asymmetric are advertised) ...

Page 188

... Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 1D4h Size: 5 DESCRIPTION 188 DATASHEET Datasheet 32 bits TYPE DEFAULT Note 13. Note 13. Note 13. Note 13.38 RO Note 13. Note 13.37 RO Note 13.39 SMSC LAN9303M/LAN9303Mi ...

Page 189

... Asymmetric Pause 0 Towards Switch Asymmetric Pause 1 Towards MAC Symmetric Pause 1 SMSC LAN9303M/LAN9303Mi DESCRIPTION and Symmetric Pause bits of the (VPHY_AN_ADV). Thus the emulated link partner always Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) configuration strap. This allows the user the choice of network emulation. ...

Page 190

... For more information on the Virtual PHY auto- Section 7.3.1, "Virtual PHY Auto-Negotiation," on page ADVERTISED LINK PARTNER ABILITY speed_strap_0 0 10BASE-T Full-Duplex (0010) 1 100BASE-X Full-Duplex (1000) 0 10BASE-T Half-Duplex (0001) 1 100BASE-X Half-Duplex (0100) 190 DATASHEET Datasheet Table 13.7 defines the Section 109. (BITS 8,7,6,5) SMSC LAN9303M/LAN9303Mi ...

Page 191

... Note 13.43 The Page Received thereafter when the Auto-Negotiation process is run. Note 13.44 The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no common bits between the advertised ability and the link partner ability). SMSC LAN9303M/LAN9303Mi 1D8h Size: 6 DESCRIPTION bit is clear when read first cleared on reset, but set shortly ...

Page 192

... Port x MAC Receive Configuration Register Isolate (VPHY_ISO) bit of the RMII/Turbo MII Clock Strength 192 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 0b Virtual is set R/W Note 13.46 bit. RO Note 13.47 R/W 0b R/W Note 13.48 NASR Note 13.51 R/W Note 13.49 NASR Note 13.51 SMSC LAN9303M/LAN9303Mi ...

Page 193

... Note 13.51 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via the Reset Control Register (VPHY_BASIC_CTRL) Note 13.52 The default value of this field is determined via the configuration strap. Refer to additional information. SMSC LAN9303M/LAN9303Mi DESCRIPTION [2] Speed 0 RESERVED 1 10Mbps 0 ...

Page 194

... This field indicates the design revision. Note 13.53 Default value is dependent on device revision. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 050h Size: DESCRIPTION 194 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 9303h RO Note 13.53 SMSC LAN9303M/LAN9303Mi ...

Page 195

... Note: In SMI mode, either half of this register can be read without the need to read the other half. BITS 31:0 Byte Test (BYTE_TEST) This field reflects the current byte ordering SMSC LAN9303M/LAN9303Mi 064h Size: DESCRIPTION 195 DATASHEET ...

Page 196

... Auto-MDIX Control (AMDIXCTRL) and 13.3.2.10). auto_mdix_strap_1 strap that connects to auto_mdix_strap_1 Auto-MDIX Control (AMDIXCTRL) and 13.3.2.10). 196 DATASHEET Datasheet 32 bits (Device Ready TYPE DEFAULT Note 13.54 Auto-MDIX RO Note 13.55 Auto-MDIX RO - for more information. for more information. SMSC LAN9303M/LAN9303Mi ...

Page 197

... RESERVED 15:0 General Purpose Timer Pre-Load (GPT_LOAD) This value is pre-loaded into the GPT. This is the starting value of the GPT. The timer will begin decrementing from this value when enabled. SMSC LAN9303M/LAN9303Mi 08Ch Size: (GPT_CNT). Refer to for additional information. DESCRIPTION 197 ...

Page 198

... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII 090h Size: General Purpose Timer Configuration Register (GPT_CFG) Section 11.1, "General Purpose Timer," on page 141 DESCRIPTION 198 DATASHEET Datasheet 32 bits to configure for additional TYPE DEFAULT FFFFh SMSC LAN9303M/LAN9303Mi ...

Page 199

... When the maximum count has been reached, the counter will rollover to zero and continue counting. Note: The free running counter can take up to 160nS to clear after a reset event. SMSC LAN9303M/LAN9303Mi 09Ch Size: for additional information. DESCRIPTION 199 ...

Page 200

... Speed Select LSB bit selects between 100Mbps RMII/Turbo MII Clock Strength 200 DATASHEET Datasheet 32 bits for additional information. TYPE DEFAULT R/W Note 13.56 bit. When RO Note 13.57 R/W 0b SMSC LAN9303M/LAN9303Mi ...