LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 49

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
4.2.1
4.2.1.1
4.2.1.2
RESET SOURCE
Digital Reset
Virtual PHY
Port 2 PHY
Port 1 PHY
nRST Pin
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire device. Configuration
straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A chip-level reset
is initiated by assertion of any of the following input events:
Chip-level reset/configuration completion can be determined by first polling the
Register
Once the returned data is the correct byte ordering value, the serial interface resets have completed.
The completion of the entire chip-level reset must then be determined by polling the
(READY)
Ready (READY)
With the exception of the
(BYTE_TEST), and
forbidden while the
Device Ready (READY)
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the device, or if the power is removed
and reapplied to the device. This event resets all circuitry within the device. Configuration straps are
latched, and the EEPROM Loader is run as a result of this reset.
A POR reset typically takes approximately 23mS, plus an additional 91uS per byte of data loaded from
the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in approximately
6.0 seconds.
nRST Pin Reset
Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the
device. Use of this reset input is optional, but when used, it must be driven for the period of time
specified in
are latched, and the EEPROM Loader is run as a result of this reset.
Power-On Reset (POR)
nRST Pin Reset
POR
(BYTE_TEST). The returned data will be invalid until the serial interface resets are complete.
bit of the
Section 14.5.2, "Reset and Configuration Strap Timing," on page
X
X
X
Table 4.1 Reset Sources and Affected Device Circuitry
bit indicates that the reset has completed and the device is ready to be accessed.
Hardware Configuration Register (HW_CFG)
Device Ready (READY)
Reset Control Register
X
X
X
bit is set.
Hardware Configuration Register
X
X
X
DATASHEET
X
X
X
X
X
49
(RESET_CTL), read access to any internal resources is
bit is cleared. Writes to any address are invalid until the
X
X
X
X
X
X
(HW_CFG),
X
X
X
until it is set. When set, the
X
X
X
Byte Order Test Register
365. Configuration straps
X
X
X
Revision 1.4 (07-07-10)
Byte Order Test
Device Ready
X
X
Device
X
X
X