LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 201

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
20:17
12:11
BITS
22
21
16
15
14
13
10
9
8
RMII Clock Direction
0: Selects P1_OUTCLK as an Input
1: Selects P1_OUTCLK as an Output
RMII/Turbo MII Clock Strength
For RMII and 200 Mbps MII PHY modes, a low selects 12 mA drive while a
high selects a 16 mA drive. For 100 Mbps and 10 Mbps MII PHY modes,
the drive strength is fixed at 12mA.
RESERVED
SQEOFF
This bit enables/disables the Signal Quality Error (Heartbeat) test.
0: SQE test enabled
1: SQE test disabled
Note:
RESERVED
Loopback
When set, transmissions from the external MAC are not sent to the Switch
Engine. Instead, they are looped back onto the receive path.
Note:
Speed Select LSB
This bit is used, along with the
0: 10 Mbps
1: 200 or 100 Mbps
Note:
RESERVED
Isolate
When set and in PHY mode, the MII output pins are not driven, the MII pull-
ups and pull-downs are disabled, and the input pins are ignored.
Note:
RESERVED
Duplex Mode
In MII and RMII PHY modes, this bit is used to set the duplex. In MII MAC
mode, this bit is used to set the duplex when the
0: Half duplex
1: Full duplex
Note:
This bit is used when Port 1 is in MII PHY mode. It is not usable
in internal PHY, RMII PHY, or MII MAC modes.
This bit is used when Port 1 is in MII or RMII PHY mode. It is not
usable in internal PHY or MII MAC modes.
This bit is used when Port 1 is in MII or RMII PHY mode. It is not
usable in internal PHY or MII MAC modes.
This bit is used when Port 1 is in MII or RMII PHY mode. It is not
usable in internal PHY or MII MAC modes.
This bit is used when Port 1 is in MII PHY, RMII PHY, or MII MAC
mode. It is not usable in internal PHY mode.
DESCRIPTION
Turbo MII Enable
DATASHEET
201
bit, to set the speed.
Manual Duplex
bit is set.
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Revision 1.4 (07-07-10)
Note 13.58
Note 13.59
Note 13.60
Note 13.61
Note 13.62
DEFAULT
0b
0b
-
-
-
-