LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 132

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Revision 1.4 (07-07-10)
9.2.4
9.2.4.1
9.2.4.2
9.2.4.3
9.2.4.4
Engine. Instead, they are looped back onto the receive path. Transmissions from the Switch Engine
are ignored and are not used for purposes of signaling data valid, collision or carrier sense on the MII
pins. The collision output to the external MAC (via P1_COL) is not generated unless the
bit is set. The SQE_HEARTBEAT signal does not drive the collision output (via P1_COL) during
External MAC loopback but can drive it during Switch Engine loopback. The carrier sense output on
the P1_CRS pin is only based on the transmit enable from the external MAC (via the P1_INDV pin).
Switch Engine loopback is enabled when the
Control Register (P1_MII_BASIC_CONTROL)
sent to the external MAC and are not used for purposes of signaling data valid, collision or carrier
sense to the MII pins. Instead, they are looped back internally onto the receive path. Transmissions
from the external MAC are ignored and are not used for purposes of data valid, collision or carrier
sense to the Switch Engine. The collision signal to the Switch Engine is not generated unless the
Switch Collision Test Port 1
from the Switch Engine. Switch Engine loopback occurs regardless of the setting of the
Port 1 RMII PHY Mode
Port 1 RMII PHY mode is used when interfacing Port 1 to an external MAC that does not support the
full MII interface. The RMII interface uses a subset of the MII pins. The P1_OUTD[1:0], P1_OUTDV,
P1_IND[1:0], P1_INDV, and P1_OUTCLK pins are the only MII pins used to communicate with the
external MAC in this mode. This mode provides collision testing for the Switch Engine, as well as
loopback test capabilities.
Note: The RMII standard does not support external MAC collision testing.
When in RMII PHY mode, if the
(P1_MII_BASIC_CONTROL)
downs are disabled and the MII data path input pins are ignored (disabled into the non-active state
and powered down). Note that setting the
pins and does not affect MII MAC mode.
Reference Clock Selection
The 50MHz RMII reference clock can be selected from either the P1_OUTCLK pin input or the internal
50MHz clock. The choice is based on the setting of the
Control Register
internal 50MHz clock. The high setting also enables P1_OUTCLK as an output to be used as the
system reference clock.
Clock Drive Strength
When P1_OUTCLK is configured as an output via the
Control Register
R M I I / Tu r b o M I I C l o c k St r e n g t h
(P1_MII_BASIC_CONTROL). A low selects 12ma, a high selects 16ma.
Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal is not generated when operating in RMII PHY mode. The
of the
RMII PHY mode.
Collision Test
External MAC collision testing is not available when operating in the RMII PHY mode. The
Test
operation in RMII PHY mode.
bit of the
Port 1 MII Basic Control Register (P1_MII_BASIC_CONTROL)
Port 1 MII Basic Control Register (P1_MII_BASIC_CONTROL)
(P1_MII_BASIC_CONTROL). A low selects P1_OUTCLK and a high selects the
(P1_MII_BASIC_CONTROL), its drive strength is based on the setting of the
bit is set. The carrier sense signal is only based on the transmit enable
is set, MII data path output pins are three-stated, the pull-ups and pull-
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
DATASHEET
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b i t o f t h e
132
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is set. Transmissions from the Switch Engine are not
Switch Looopback Port 1
bit of the
bit does not cause isolation of the MII management
RMII Clock Direction
RMII Clock Direction
P o r t 1 M I I B a s i c C o n t r o l R e g i s t e r
Port 1 MII Basic Control Register
has no effect when operating in
bit of the
SMSC LAN9303M/LAN9303Mi
bit of the
bit of the
has no effect on system
Port 1 MII Basic
Port 1 MII Basic
Port 1 MII Basic
Collision Test
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SQEOFF
Datasheet
Collision
bit.
bit