LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 28

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Revision 1.4 (07-07-10)
PINS
NUM
1
1
1
Port 1 Mode[2]
Port 1 Mode[1]
Output Data 3
Output Data 2
Output Data 1
Port 1 Duplex
Configuration
Configuration
Configuration
Port 1 MII
Port 1 MII
Port 1 MII
Polarity
NAME
Strap
Strap
Strap
DUPLEX_POL_1
P1_MODE2
P1_MODE1
P1_OUTD3
P1_OUTD2
P1_OUTD1
SYMBOL
Table 3.4 Port 1 MII/RMII Pins (continued)
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
DATASHEET
BUFFER
Note 3.5
Note 3.5
Note 3.5
TYPE
(PU)
(PU)
(PU)
O8
O8
O8
O8
O8
O8
O8
IS
IS
IS
-
-
-
-
-
28
MII MAC Mode: This pin is the transmit data 3 bit
from the switch to the external PHY.
MII PHY Mode: This pin is the receive data 3 bit
from the switch to the external MAC. The output
driver is disabled when the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is not used.
Internal PHY Mode: This pin is not used.
This strap selects the default of the duplex polarity
strap for Port 1 MII (duplex_pol_strap_1) and is
used only in MII PHY, RMII PHY, and MII MAC
modes. See
If the strap is value is 0, a 0 on P1_DUPLEX
means full duplex while a 1 means half duplex. If
the strap value is 1, a 1 on P1_DUPLEX means full
duplex, while a 0 means half duplex.
MII MAC Mode: This pin is the transmit data 2 bit
from the switch to the external PHY.
MII PHY Mode: This pin is the receive data 2 bit
from the switch to the external MAC. The output
driver is disabled when the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is not used.
Internal PHY Mode: This pin is not used.
This strap configures the mode for the Port 1 MII
pins. See
Please refer to the
mode encoding details.
MII MAC Mode: This pin is the transmit data 1 bit
from the switch to the external PHY.
MII PHY Mode: This pin is the receive data 1 bit
from the switch to the external MAC. The output
driver is disabled when the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is the receive data 1 bit
from the switch to the external MAC. The output
driver is disabled when the
Port 1 MII Basic Control Register
(P1_MII_BASIC_CONTROL).
Internal PHY Mode: This pin is not used.
This strap configures the mode for the Port 1 MII
pins. See
Please refer to the
mode encoding details.
Note
Note
Note
3.4.
3.4.
DESCRIPTION
3.4.
P1_MODE0
P1_MODE0
SMSC LAN9303M/LAN9303Mi
Isolate
Isolate
Isolate
Isolate
strap entry for
strap entry for
bit is set in the
bit is set in the
bit is set in the
bit is set in the
Datasheet