LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 130

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Revision 1.4 (07-07-10)
9.1.3.2
9.1.3.3
9.1.3.4
9.1.3.5
9.2
9.2.1
9.2.2
and a high selects the internal 50MHz clock. The high setting also enables P0_OUTCLK as an output
to be used as the system reference clock.
Clock Drive Strength
When P0_OUTCLK is configured as an output via the
Special Control/Status Register
the setting of the
(VPHY_SPECIAL_CONTROL_STATUS). A low selects 12ma, a high selects 16ma.
Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal is not generated when operating in RMII PHY mode. The
of the
effect when operating in RMII PHY mode.
Collision Test
External MAC collision testing is not available when operating in the RMII PHY mode. The
Test (VPHY_COL_TEST)
effect on system operation in RMII PHY mode.
Switch Engine collision testing is available and is enabled when the
the
test mode, any transmissions from the Switch Engine will result in the assertion of an internal collision
signal to the Switch Fabric Port 0. Switch Engine collision test occurs regardless of the setting of the
Isolate (VPHY_ISO)
Loopback Mode
Two forms of loopback testing are available: External MAC loopback and Switch Engine loopback.
External MAC loopback is enabled when the
Basic Control Register (VPHY_BASIC_CTRL)
sent to the Switch Engine. Instead, they are looped back onto the receive path. Transmissions from
the Switch Engine are ignored.
Switch Engine loopback is enabled when the
Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
Engine are not sent to the external MAC. Instead, they are looped back internally onto the receive
path. Transmissions from the external MAC are ignored. An internal collision signal to the Switch
Engine is available and is asserted when the
loopback occurs regardless of the setting of the
The MII MUX/Data Path is used to connect the Switch Engine port to the external MII pins, to emulate
an RMII/MII PHY, and to select between PHY and MAC modes.
Port 1 Internal Mode
When operating in Internal mode, the Switch Fabric MAC outputs are directly connected to the internal
PHY. Similarly, the Switch Fabric Mac inputs are sourced from the internal PHY.
Port 1 MII MAC Mode
When operating in MII MAC mode, the Switch Fabric MAC output signals are routed directly to the
device’s MII output pins (P1_OUTD[3:0] and P1_OUTDV). The Switch Fabric MAC inputs are sourced
Port 1 MII MUX/Data Path
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
RMII/Turbo MII Clock Strength
bit.
bit of the
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
(VPHY_SPECIAL_CONTROL_STATUS), its drive strength is based on
DATASHEET
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
130
Switch Looopback Port 0
Loopback (VPHY_LOOPBACK)
is set. Transmissions from the external MAC are not
Switch Collision Test Port 0
bit of the
Isolate (VPHY_ISO)
RMII Clock Direction
Virtual PHY Special Control/Status Register
is set. Transmissions from the Switch
Switch Collision Test Port 0
bit.
bit of the
SMSC LAN9303M/LAN9303Mi
bit is set. Switch Engine
bit of the
bit of the
Virtual PHY Special
is set. In this
SQEOFF
Virtual PHY
Virtual PHY
Datasheet
Collision
has no
has no
bit of
bit