LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 125

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
8.5
8.5.1
3. The EEPROM Loader writes select Port 1/2 and Virtual PHY registers, as specified in
Note: Step 3 is also performed in the case of a RELOAD command or digital reset.
When in MAC/PHY I
device. All system CSRs are accessible to the CPU in these modes. I
mngt_mode_strap[1:0]
implements the low level I
transmission and reception, and acknowledge generation and reception), handles the slave command
protocol, and performs system register reads and writes. The I
I
The I
is driven by the master, while the data wire is bi-directional. Both signals are open-drain and require
external pull-up resistors.
The I
speed of 400KHz. Refer to the NXP I
I
The I
A read or write command is started by the master first sending a start condition, followed by a control
byte. The control byte consists of a 7-bit slave address and a 1-bit read/write indication (R/~W). The
slave address used by the device is 0001010b, written as SA6 (first bit on the wire) through SA0 (last
bit on the wire). Assuming the slave address in the control byte matches this address, the control byte
is acknowledged by the device. Otherwise, the entire sequence is ignored until the next start condition.
The I
If the read/write indication (R/~W) in the control byte is a 0 (indicating a potential write), the next byte
sent by the master is the register address. After the address byte is acknowledged by the device, the
master may either send data bytes to be written, or it may send another start condition (to start the
reading of data), or a stop condition. The latter two will terminate the current write (without writing any
data), but will have the affect of setting the internal register address which will be used for subsequent
reads.
If the read/write indication in the control byte is a 1 (indicating a read), the device will start sending
data following the control byte acknowledgement.
Note: All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the
I
2
2
2
C-Bus Specification .
C Slave Command Format
C Slave Operation
Section 8.4.4.1
2
2
2
2
C slave serial interface consists of a data wire (SDA) and a serial clock (SCL). The serial clock
C slave serial interface supports single register and multiple register read and write commands.
C command format can be seen in
C slave serial interface supports the standard-mode speed of up to 100KHz and the fast-mode
register address. Addresses and data are transferred msb first. Data is transferred MSB first
(little endian).
S
S
A
6
S
A
5
Control Byte
and
S
A
2
4
C managed mode, the I
Section
configuration straps are set to 10b, respectively. The I
S
A
3
Figure 8.8 I
S
A
2
2
C slave serial interface (start and stop condition detection, data bit
S
A
1
8.4.4.2, respectively.
S
A
0
R/~W
DATASHEET
2
0
2
C-Bus Specification for detailed I
C Slave Addressing
A
C
K
125
Figure
A
9
2
C slave interface is used for CPU management of the
A
8
Address Byte
8.8.
A
7
A
6
A
5
Data [31]
Start or
Stop or
2
A
4
C slave controller conforms to the NXP
A
3
A
2
2
2
C mode is selected when the
A
C
K
C timing information.
*
Revision 1.4 (07-07-10)
2
C slave controller