LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 143

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
12.2.1.1
12.3
(GPIO5)
(GPIO4)
(GPIO3)
(GPIO2)
LED5
LED4
LED3
LED2
GPIO Interrupt Polarity
The interrupt polarity can be set for each individual GPIO via the
(GPIO_INT_POL[5:0])
a high logic level on the GPIO pin will set the corresponding interrupt bit in the
Interrupt Status and Enable Register
GPIO pin will set the corresponding interrupt bit.
Each GPIO can be individually selected to function as a LED. These pins are configured as LED
outputs by setting the corresponding
Register
source output and the GPIO related input buffer and pull-up are disabled. The default configuration,
including polarity, is determined by input straps or EEPROM entries. Refer to
page 51
The functions associated with each LED pin are configurable via the
bits of the
to indicate various port related functions. These functions are described in
detailed definition of each indication type.
The default values of the
of the
LED_en_strap[5:0]
(LED_CFG)
on page
LED Operation
(if Port 1 internal PHY
(if Port 1 internal PHY
Full-duplex / Collision
LED Configuration Register (LED_CFG)
Link / Activity
Link / Activity
157.
for additional information.
(LED_CFG). When configured as a LED, the pin is either a push-pull or open-drain / open-
disabled)
enabled)
LED Configuration Register
Activity
Speed
Port 2
Port 2
Port 2
Port 1
Port 1
and its related straps, refer to
00b
Table 12.1 LED Operation as a Function of LED_FUN[1:0]
configuration straps. For more information on the
bits in the
LED Function 1-0 (LED_FUN[1:0])
(if Port 1 internal PHY
(if Port 1 internal PHY
Full-duplex / Collision
100Link / Activity
100Link / Activity
10Link / Activity
General Purpose I/O Configuration Register
DATASHEET
disabled)
enabled)
Activity
Port 2
Port 2
Port 2
Port 1
Port 1
01b
(GPIO_INT_STS_EN). When cleared, a low logic level on the
(LED_CFG). These bits allow the configuration of each LED pin
LED Enable 5-0 (LED_EN[5:0])
143
Section 13.2.2.4, "LED Configuration Register (LED_CFG),"
are determined by the
Link / Activity
Speed
Port 0
Port 2
Port 2
Port 0
and
10b
RX
TX
LED Enable 5-0 (LED_EN[5:0])
LED Function 1-0 (LED_FUN[1:0])
bit in the
GPIO Interrupt Polarity 5-0
LED Configuration Register
LED_fun_strap[1:0]
Table
(GPIO_CFG). When set,
Configuration Straps on
General Purpose I/O
Revision 1.4 (07-07-10)
12.1, followed by a
LED Configuration
RX_DV
RX_DV
TX_EN
TX_EN
Port 0
Port 2
Port 2
Port 0
11b
and
bits