LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 122

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Revision 1.4 (07-07-10)
8.4.2
8.4.3
8.4.4
8.4.4.1
BYTE/BIT
Byte 10
Byte 11
Byte 8
Byte 9
EEPROM Valid Flag
Following the release of nRST, POR, DIGITAL_RST, or a RELOAD command, the EEPROM Loader
starts by reading the first byte of data from the EEPROM. If the value of A5h is not read from the first
byte, the EEPROM Loader will load the current configuration strap values into the PHY registers (see
Section
EEPROM Command Register
sequential bytes from the EEPROM.
MAC Address
The next six bytes in the EEPROM, after the EEPROM Valid Flag, are written into the
MAC Address High Register (SWITCH_MAC_ADDRH)
(SWITCH_MAC_ADDRL). The EEPROM bytes are written into the MAC address registers in the order
specified in
Soft-Straps
The 7
byte has a value of A5h, the next 4 bytes of data (8-11) are written into the configuration strap registers
per the assignments detailed in
(they are still read to maintain the data burst, but are discarded). However, the current configuration
strap values are still loaded into the PHY registers (see
"Configuration Straps," on page 51
PHY Registers Synchronization
Some PHY register defaults are based on configuration straps. In order to maintain consistency
between the updated configuration strap registers and the PHY registers, the
Negotiation Advertisement Register
(PHY_SPECIAL_MODES_x), and
written when the EEPROM Loader is run.
The
defaults as detailed in
(PHY_AN_ADV_x)," on page
The
as detailed in
page
BP_EN_
BP_EN_
strap_1
strap_2
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
LED_fun_strap[1:0]
7
219.
th
8.4.4.1) and then terminate, clearing the
byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this
unused
Table
Section 13.3.2.9, "Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)," on
FD_FC_
FD_FC_
strap_1
strap_2
6
8.2.
Table 8.3 EEPROM Configuration Bits
Section 13.3.2.5, "Port x PHY Auto-Negotiation Advertisement Register
FC_strap_1
FC_strap_2
manual_
manual_
BP_EN_
strap_0
212.
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
5
(E2P_CMD). Otherwise, the EEPROM Loader will continue reading
Table
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
DATASHEET
for more information on configuration straps.
8.3. If the flag byte is not A5h, these next 4 bytes are skipped
manual_mdix
manual_mdix
(PHY_AN_ADV_x),
_strap_1
_strap_2
FD_FC_
strap_0
122
4
EEPROM Controller Busy (EPC_BUSY)
auto_mdix_
auto_mdix_
manual_FC
_strap_0
strap_1
strap_2
and
LED_en_strap[5:0]
3
Switch Fabric MAC Address Low Register
Section
Port x PHY Special Modes Register
speed_
strap_1
speed_
strap_2
speed_
strap_0
8.4.4.1). Refer to
2
is written with the new defaults
SMSC LAN9303M/LAN9303Mi
duplex_pol_
duplex_pol_
strap_1 /
is written with the new
duplex_
duplex_
strap_1
strap_2
strap_0
1
Port x PHY Auto-
Section 4.2.4,
Switch Fabric
disable_strap
disable_strap
SQE_test_
SQE_test_
autoneg_
autoneg_
strap_1/
strap_2
Datasheet
bit in the
_1
_0
0
are