LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 96

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Revision 1.4 (07-07-10)
7.2
To MII Mux
To Port x
Switch Fabric MAC
The Port 1 and Port 2 PHYs are functionally identical. The Port 1 PHY is active when Port 1 is
operating in Internal PHY mode. The Port 1 PHY may optionally be bypassed for the connection of an
external MAC or PHY via the Port 1 MII/RMII interface. Each PHY can be divided into the following
functional sections:
Note 7.1
A block diagram of the Port x PHYs main components can be seen in
Port 1 & 2 PHYs
MDIO
MII
100BASE-TX Transmit
10BASE-T Transmit
PHY Auto-negotiation
HP Auto-MDIX
MII MAC Interface
PHY Management Control
Registers
Interface
PHY Management
Negotiation
Because the Port 1 PHY and Port 2 PHY are functionally identical, this section will describe
them as the “Port x PHY”, or simply “PHY”. Wherever a lowercase “x” has been appended
to a port or signal name, it can be replaced with “1” or “2” to indicate the Port 1 or Port 2
PHY respectively. All references to “PHY” in this section can be used interchangeably for
both the Port 1 & 2 PHYs. This nomenclature excludes the Virtual PHY.
MAC
MII
Auto-
Control
Interrupt Controller
To System
Interrupts
Figure 7.1 Port x PHY Block Diagram
and
and
10BASE-T Receive
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
100BASE-TX Receive
Transmitter
Reciever
10/100
10/100
DATASHEET
To GPIO/LED
96
Controller
LEDs
HP Auto-MDIX
From
System Clocks Controller
PLL
Figure
TXPx/TXNx
RXPx/RXNx
SMSC LAN9303M/LAN9303Mi
7.1.
To External
Port x Ethernet Pins
Datasheet