LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 219

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
13.3.2.9
BITS
15:8
7:5
4:0
RESERVED
PHY Mode (MODE[2:0])
This field reflects the default PHY mode of operation. Refer to
for a definition of each mode.
PHY Address (PHYADD)
The PHY Address field determines the MMI address to which the PHY will
respond and is also used for initialization of the cipher (scrambler) key. Each
PHY must have a unique address. Refer to
Addressing," on page 95
Note:
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
This read/write register is used to control the special modes of the Port x PHY.
Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD
Note 13.72 Register bits designated as NASR are reset when the Port x PHY Reset is generated via
Note 13.73 For Port 1 operating in an external mode (MII PHY, RMII PHY, or MII MAC mode), the
Note 13.74 The default value of this field is determined by the
No check is performed to ensure this address is unique from the
other PHY addresses (Port 1 PHY, Port 2 PHY, and Virtual PHY).
command. Refer to
Index (decimal): 18
the
t h e
(PHY_BASIC_CONTROL_x)
default value of this field is 110b and is independent of any strap. For Port 1 operating in
Internal PHY mode and for all operating modes of Port 2, the default value of this field is
determined by a combination of the configuration straps autoneg_strap_x, speed_strap_x,
and duplex_strap_x. If the autoneg_strap_x is 1, then the default MODE[2:0] value is 111b.
Else, the default value of this field is determined by the remaining straps. MODE[2]=0,
MODE[1]=(speed_strap_1
MODE[0]=(duplex_strap_1
strap values are latched upon the de-assertion of a chip-level reset as described in
4.2.4, "Configuration Straps," on page
on page 51
Refer to
Reset Control Register
R e s e t ( P H Y _ R S T )
Section 7.1.1, "PHY Addressing," on page 95
for additional information.
for strap definitions.
DESCRIPTION
Section 8.4, "EEPROM Loader," on page 120
DATASHEET
(RESET_CTL). The NASR designation is only applicable when
for Port 1 PHY,
is set.
for Port 1 PHY,
Section 7.1.1, "PHY
b i t o f t h e
219
Size:
51. Refer to
duplex_strap_2
P o r t x P H Y B a s i c C o n t r o l R e g i s t e r
speed_strap_2
Table 13.11
phy_addr_sel_strap
16 bits
Section 4.2.4, "Configuration Straps,"
for additional information.
for Port 2 PHY). Configuration
for more information.
Note 13.72
Note 13.72
NASR
NASR
TYPE
for Port 2 PHY), and
R/W
R/W
RO
Revision 1.4 (07-07-10)
configuration strap.
DEFAULT
Note 13.73
Note 13.74
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Section