ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet
ADSP-21362WBBCZ-1A
Related parts for ADSP-21362WBBCZ-1A
ADSP-21362WBBCZ-1A Summary of contents
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... Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The ADSP-2136x processors are available with a 333 MHz core instruction rate and unique peripherals such as the digi- tal audio interface, S/PDIF transceiver, DTCP (digital ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 KEY FEATURES—PROCESSOR CORE At 333 MHz (3.0 ns) core instruction rate, the ADSP-2136x performs 2 GFLOPS/666 MMACs 3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit in blocks 2 and 3) for simultaneous access by the core pro- cessor and DMA 4M bit on-chip ROM (2M bit in block 0 and 2M bit in block 1) ...
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... Core Clock and System Clock Relationship to CLKIN .................................................................18 Fixed Figure 24, This version of the data sheet is for BGA parts only. An alternate LQFP package (exposed pad) will be available in the future. Information on that option is available on the ADSP-21365 product page. See Rev Page December 2006 4. IDP Master Timing ............................34 Ordering Guide ...............................52 ...
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... The ADSP-2136x SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Har- vard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (sin- gle-instruction, single-data) mode. The ADSP-2136x is a ...
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... DAI SHARC FAMILY CORE ARCHITECTURE The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as detailed in the following sections ...
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... Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-2136x can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction ...
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... In this case, the instruction must be available in the cache. DMA Controller The ADSP-2136x’s on-chip DMA controllers allow data trans- fers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simulta- neously executing its program instructions. DMA transfers can occur between the processor’ ...
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... The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-2136x SPI- compatible peripheral implementation also features program- mable baud rate, clock phase, and polarities. The SPI- compatible port uses open drain drivers to support a multimas- ter configuration and to avoid data contention ...
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... PWM patterns that produce lower harmonic dis- tortion in three-phase PWM inverters. Timers The ADSP-2136x has a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes: • ...
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... For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro- priate “Emulator Hardware User’s Guide.” DEVELOPMENT TOOLS The ADSP-2136x is supported with a complete set of ®† CROSSCORE software and hardware development tools, including Analog Devices emulators and VisualDSP++ opment environment ...
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... ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2136x architecture and functionality. For detailed infor- mation on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference. ®† ...
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... A23–8; ALE is used in conjunction with an external latch to retain the values of the A23–8. For detailed information on I/O operations and pin multiplexing, see the ADSP-2136x SHARC Processor Hardware Reference. Parallel Port Read Enable asserted low whenever the processor reads 8-bit or 16-bit data from an external memory device. When AD15– ...
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... SPI interaction, any of the master processor’s flag pins can be used to drive the SPIDS signal on the SPI slave device. SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2136x. TRST has a 22.5 kΩ internal pull-up resistor. Emulation Status. Must be connected to the processor’s JTAG emulators target board connector only. EMU has a 22.5 kΩ ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ADDRESS DATA PINS AS FLAGS To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the SYSCTL register to disable the parallel port. Then set (=1) Bits the SYSCTL register accordingly. Table 5. AD15–0 to Flag Pin Mapping AD Pin Flag Pin AD Pin AD0 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ADSP-2136x SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ CLKIN V Low Level Input Voltage @ V ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2136x features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TIMING SPECIFICATIONS The ADSP-2136x’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1– ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Power-Up Sequencing The timing requirements for processor startup are given in Table 12. Table 12. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT 1 t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST ...
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... Jitter specification is maximum peak-to-peak time interval error (TIE) jitter Clock Signals The ADSP-2136x can use an external clock or a crystal. See the CLKIN pin description in Table 4 on Page tion program can configure theADSP-2136x to use its internal clock generator by connecting the necessary components to the CLKIN and XTAL pins ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Reset Table 14. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 16. Core Timer Parameter Switching Characteristic t CTIMER Pulse Width WCTIM FLAG3 (CTIMER) Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins. ...
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... PCG Output Clock Delay After PCG Trigger DTRIGCLK t PCG Frame Sync Delay After PCG Trigger DTRIGFS t Output Clock Period PCGOP D = FSxDIV FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter normal mode, t (min × PCGOP PCGIP ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 4, “Pin Descriptions,” on Page 12 more information on flag use. Table 21. Flags Parameter Timing Requirement t FLAG3–0 IN Pulse Width ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-2136x is accessing external memory space. Table 22. 8-Bit Memory Read Cycle Parameter Timing Requirements 1 t AD7–0 Data Setup Before RD High DRS t AD7–0 Data Hold After RD High ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 t ALERW t ALE ALEW ADAS ADAH AD15-8 VALID ADDRESS VALID ADDRESS AD7-0 t ALEHZ NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY READS IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION. Figure 18. Read Cycle for 8-Bit Memory Timing Rev ...
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... On reset, ALE is an active high cycle. However, it can be configured by software to be active low. 2 This parameter is only available when in EMPP = 0 mode. ALE RD WR AD15 - 0 NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP WHEN EMPP = 0, MULTIPLE SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE. t ALERW t ALEW t RRH t RW ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-2136x is accessing external memory space. Table 24. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW 1 t AD15–0 Address Setup Before ALE Deasserted ...
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... On reset, ALE is an active high cycle. However, it can be configured by software to be active low. 2 This parameter is only available when in EMPP = 0 mode. ALE WR RD AD15 - 0 NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP WHEN EMPP = 0, MULTIPLE SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE ALEW ALERW WRH ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 26. Serial Ports—External Clock ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 28. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 29. Serial Ports—External Late Frame Sync ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW DAI_P20 - 1 (SCLK) t DFSIR t t HOFSR DAI_P20 - 1 (FS) t SDRI DAI_P20 - 1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Input Data Port (IDP) The timing requirements for the IDP are given in signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 30. IDP Parameter Timing Requirements ...
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... The timing requirements for the PDAP are provided in Table 31. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2136x SHARC Processor Table 31. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
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... The SRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing spec- ifications provided in Table 33 are valid at the DAI_P20–1 pins. This feature is not available on the ADSP-21363 models. Table 33. SRC, Serial Input Port Parameter Timing Requirements 1 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge ...
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... SPDIF Transmitter Serial data input to the SPDIF transmitter can be formatted as 2 left-justified right-justified with word widths of 16, 18, 20 bits. The following sections provide timing for the transmitter. This feature is not available on the ADSP-21363 models. LRCLK SCLK SDATA LSB MSB 2 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPDIF Transmitter Input Data Timing The timing requirements for the input port are given in Table 35. Input signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing spec- ifications provided below are valid at the DAI_P20–1 pins. ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPDIF Receiver The following section describes timing as it relates to the SPDIF receiver. This feature is not available on the ADSP-21363 models. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 37. SPDIF Receiver Output Timing (Internal Digital PLL Mode) ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Master The ADSP-2136x contains two SPI ports. The primary has dedi- cated pins and the secondary is available through the DAI. The timing provided in Table 38 and Table 39 Table 38. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 FLAG3-0 (OUTPUT SPICLK ( (OUTPUT) SPICLK ( (OUTPUT) MOSI (OUTPUT) CPHASE = 1 MISO (INPUT) MOSI (OUTPUT CPHASE = 0 MSB MISO VALID (INPUT ...
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... SPIDS Assertion to Data Out Valid (CPHASE = 0) DSOV 1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter. Min 4 × × × ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPIDS (INPUT SPICLK ( (INPUT SPICLK ( (INPUT MISO (OUTPUT) t CPHASE = MOSI (INPUT MISO MSB (OUTPUT) CPHASE = 0 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 JTAG Test Access Port and Emulation Table 40. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK High ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTPUT DRIVE CURRENTS Figure 37 shows typical I-V characteristics for the output driv- ers of the ADSP-2136x. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, +125° 3.11V, +125° 3.47V, - 45° ...
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... LOAD CAPACITANCE (pF) Figure 42. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-2136x processor is rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 41 and Table 42 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 136-BALL BGA PIN CONFIGURATIONS The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 43. BGA Pin Assignments Ball Name Ball No. Ball Name CLKCFG0 A01 CLKCFG1 XTAL A02 GND TMS A03 V DDEXT TCK A04 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 43. BGA Pin Assignments (Continued) Ball Name Ball No. Ball Name AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) J14 ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 KEY V * DDINT GND V A DDEXT VSS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 43. BGA Pin Assignments (Bottom View, Summary ...
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... ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTLINE DIMENSIONS The ADSP-2136x is available in a 136-ball BGA package. 12.00 BSC SQ PIN A1 INDICATOR TOP VIEW 1.70 MAX 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0. ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR THE BALL DIAMETER ...
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... ADSP-21362KBCZ-1AA 0°C to +70°C ADSP-21362BBC-1AA –40°C to +85°C 333 MHz 2 ADSP-21362BBCZ-1AA –40°C to +85°C 333 MHz 2 ADSP-21362WBBCZ-1A –40°C to +85°C 333 MHz ADSP-21363KBC-1AA 0°C to +70°C 2 ADSP-21363KBCZ-1AA 0°C to +70°C ADSP-21363BBC-1AA –40°C to +85°C 333 MHz 2 ADSP-21363BBCZ-1AA – ...