ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 39

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

SPDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided below are valid at the DAI_P20–1 pins.
Table 35. SPDIF Transmitter Input Data Timing
1
Oversampling Clock (TXCLK) Switching Characteristics
SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the biphase clock.
Table 36. Oversampling Clock (TXCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Parameter
TXCLK Frequency for TXCLK = 768 × FS
TXCLK Frequency for TXCLK = 512 × FS
TXCLK Frequency for TXCLK = 384 × FS
TXCLK Frequency for TXCLK = 256 × FS
Frame Rate
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
SISCLKW
SISCLK
SITXCLKW
SITXCLK
1
1
1
1
35. Input signals (SCLK, FS, and SDATA) are routed to
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
Transmit Clock Width
Transmit Clock Period
SAMPLE EDGE
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
(TXCLK)
(SDATA)
(SCLK)
(FS)
Figure 32. SPDIF Transmitter Input Timing
Rev. A | Page 39 of 52 | December 2006
t
SITXCLKW
t
SISCLKW
Min
3
3
36
80
20
3
3
9
t
SISFS
t
SISD
Min
t
SITXCLK
Max
t
t
SIHFS
SIHD
Max
147.5
98.4
73.8
49.2
192.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
MHz
MHz
MHz
kHz