ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 21

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ADSP-21362WBBCZ-1A

Manufacturer Part Number
ADSP-21362WBBCZ-1A
Description
SHARC Processor
Manufacturer
AD [Analog Devices]
Datasheet
Reset
Table 14. Reset
1
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 15. Interrupts
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
Parameter
Timing Requirement
t
WRST
SRST
V
IPW
DD
1
and CLKIN (not including start-up time of external clock oscillator).
IRQx Pulse Width
RESET Pulse Width Low
RESET Setup Before CLKIN Low
RESET
CLKIN
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
FLAG2
DAI20
(IRQ2 - 0)
Rev. A | Page 21 of 52 | December 2006
-
-
1
0
Figure 11. Interrupts
Figure 10. Reset
t
WRST
t
IPW
Min
4t
8
CK
Min
2 × t
PCLK
+2
t
SRST
Max
Max
Unit
ns
Unit
ns
ns

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