ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 36

no-image

ADSP-21362WBBCZ-1A

Manufacturer Part Number
ADSP-21362WBBCZ-1A
Description
SHARC Processor
Manufacturer
AD [Analog Devices]
Datasheet
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Pulse-Width Modulation Generators
Table 32. PWM Timing
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in
This feature is not available on the ADSP-21363 models.
Table 33. SRC, Serial Input Port
1
Parameter
Switching Characteristics
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
PWMW
PWMP
SRCSFS
SRCHFS
SRCSD
SRCHD
SRCCLKW
SRCCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
PWM Output Pulse Width
PWM Output Period
OUTPUTS
Table 33
PWM
are valid at the DAI_P20–1 pins.
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
(SDATA)
(SCLK)
(FS)
Rev. A | Page 36 of 52 | December 2006
Figure 27. SRC Serial Input Port Timing
t
PWMW
Figure 26. PWM Timing
t
SRCCLKW
t
t
SRCSFS
PWMP
t
Min
t
2 × t
SRCSD
PCLK
– 2
PCLK
t
SRCCLK
SAMPLE EDGE
– 1.5
t
SRCHFS
t
SRCHD
Min
3
3
3
3
36
80
Max
(2
(2
16
16
– 2) × t
– 1) × t
Max
PCLK
PCLK
– 2
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns

Related parts for ADSP-21362WBBCZ-1A