ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 30

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 25. 16-Bit Memory Write Cycle
1
2
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
F = 7 × t
t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
This parameter is only available when in EMPP = 0 mode.
ALEW
ADAS
ALERW
RWALE
WRH
ADAH
WW
DWS
DWH
PCLK
2
1
1
= (peripheral) clock period = 2 × t
PCLK
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × t
AD15 - 0
NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP
WHEN EMPP = 0, MULTIPLE
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
ALE
WR
RD
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
AD15–0 Data Setup Before WR High
AD15–0 Data Hold After WR High
CCLK
t
WR
ALEW
t
ADAS
PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
ADDRESS
VALID
Figure 21. Write Cycle for 16-Bit Memory Timing
Rev. A | Page 30 of 52 | December 2006
t
ADAH
t
ALERW
0, ONLY ONE
VALID DATA
t
DWS
t
WW
WR
PULSE OCCURS BETWEEN ALE CYCLES.
t
DWH
t
WRH
PCLK
VALID DATA
.
PCLK
t
D – F – 2.0
Min
2 × t
t
2 × t
H + 0.5
F + H + t
D – F + t
H
t
PCLK
PCLK
RWALE
.
– 2.5
– 2.3
PCLK
PCLK
– 2.0
– 3.8
PCLK
PCLK
– 4.0
– 2.3
ADDRESS
VALID
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns