ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 40

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPDIF Receiver
The following section describes timing as it relates to the SPDIF
receiver. This feature is not available on the
ADSP-21363 models.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 37. SPDIF Receiver Output Timing (Internal Digital PLL Mode)
1
Parameter
Switching Characteristics
t
t
t
t
t
t
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
CCLK
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
Core Clock Period
(DATA CHANNEL A/B)
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing
(SCLK)
(FS)
Rev. A | Page 40 of 52 | December 2006
DRIVE EDGE
t
t
HOFSI
HDTI
t
DFSI
t
SCLKIW
t
DDTI
Min
–2
–2
38
SAMPLE EDGE
Max
5
5
5
Unit
ns
ns
ns
ns
ns
ns