ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 37

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and should
meet setup and hold times with regard to SCLK on the output
port. The serial data output, SDATA, has a hold time and delay
specification with regard to SCLK. Note that SCLK rising edge is
the sampling edge and the falling edge is the drive edge.
Table 34. SRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SRCSFS
SRCHFS
SRCTDD
SRCTDH
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
(SDATA)
(SCLK)
(FS)
Figure 28. SRC Serial Output Port Timing
t
Rev. A | Page 37 of 52 | December 2006
SRCTDH
t
SRCTDD
t
SRCCLKW
SAMPLE EDGE
t
SRCSFS
t
SRCHFS
t
SRCCLK
3
Min
3
2
Max
10.5
Unit
ns
ns
ns
ns