ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 18

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
TIMING SPECIFICATIONS
The ADSP-2136x’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor’s internal clock frequency and
external (CLKIN) clock frequency with the CLKCFG1–0 pins
(see
for the serial ports, divide down the internal clock, using the
programmable divider control of each port (DIVx for the
serial ports).
The ADSP-2136x’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock (the
clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control shown in
and
Table 10. ADSP-2136x Clock Generation Operation
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
Timing
Requirements
CLKIN
CCLK
Table
XTAL
Table 8 on Page
CLKIN
RESET
11.
XTAL
OSC
15). To determine switching frequencies
Description
Input Clock
Core Clock
INDIV
÷1, 2
Calculation
1/t
1/t
Figure 6. Core Clock and System Clock Relationship to CLKIN
PLLICLK
CK
CCLK
Rev. A | Page 18 of 52 | December 2006
CLK_CFG [1:0]
(6:1, 16:1, 32:1)
Table 10
PLLM
DELAY
÷2, 4, 8, 16
DIVEN
Table 11. Clock Periods
1
Figure 6
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2136x SHARC Processor Programming Reference.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 39 on Page 46
reference levels.
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing
Requirements
t
t
t
t
t
where:
SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT
CK
CCLK
PCLK
SCLK
SPICLK
CLKDIV)
SPIR = SPI-to-peripheral clock ratio (wide range, determined by SPIBAUD
register)
DAI_Px = serial port clock
SPICLK = SPI clock
shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
RESETOUT
CLKOUT
OR
CCLK
(CORE CLOCK)
under Test Conditions for voltage
Description
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × t
Serial Port Clock Period = (t
SPI Clock Period = (t
÷ 2
1
PCLK
(PERIPHERAL CLOCK)
PCLK
) × SPIR
PCLK
) × SR
CCLK