ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 20

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Clock Input
Table 13. Clock Input
1
2
3
4
Clock Signals
The ADSP-2136x can use an external clock or a crystal. See the
CLKIN pin description in
tion program can configure theADSP-2136x to use its internal
clock generator by connecting the necessary components to the
CLKIN and XTAL pins.
tions used for a fundamental frequency crystal operating in
parallel mode.
Note that the clock rate is achieved using a 16.67 MHz crystal
and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock
speed of 266.72 MHz). To achieve the full core clock rate, pro-
grams need to configure the multiplier bits in the
PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
t
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
Actual input jitter should be combined with ac specifications for accurate timing analysis.
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
CK
CKL
CKH
CKRF
CCLK
CKJ
3,4
2
C LK IN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
CLKIN Jitter Tolerance
Figure 9
Table 4 on Page
shows the component connec-
t
C K H
12. The user applica-
t
C K
Rev. A | Page 20 of 52 | December 2006
Figure 8. Clock Input
t
C K L
CCLK
Min
18
7.5
7.5
3.0
–250
C1
22pF
Figure 9. 333 MHz Operation (Fundamental Mode Crystal)
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
1
.
1
1
1
CLKIN
t
C K J
24.576MHz
R1
1M *
333 MHz
Y1
ADSP-2136X
Max
100
3
10
+250
XTAL
R2
47 *
C2
22pF
Unit
ns
ns
ns
ns
ns
ps