ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 19

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Power-Up Sequencing
The timing requirements for processor startup are given in
Table
Table 12. Power-Up Sequencing Timing Requirements (Processor Startup)
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
milliseconds depending on the design of the power supply subsystem.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
cycles maximum.
12.
1
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of
CLK_CFG1-0
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
V
RSTOUT
V
DDINT
DDEXT
RESET
DDINT
CLKIN
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SRST
On Before V
specification in
t
DDEXT
RSTVDD
DDINT
DDINT
Table
/V
/V
DDEXT
DDEXT
14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
Rev. A | Page 19 of 52 | December 2006
Valid
On
Figure 7. Power-Up Sequencing
t
IVDDEVDD
t
CLKVDD
t
PLLRST
t
CLKRST
Min
0
–50
0
10
20
4096t
t
2
CORERST
CK
+ 2 t
CCLK
3, 4
Max
+200
+200
Unit
ns
ms
ms
μs
μs