ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 26

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the ADSP-2136x
is accessing external memory space.
Table 22. 8-Bit Memory Read Cycle
1
2
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
F = 7 × t
t
The timing specified here is sufficient to satisfy either t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
DRS
DRH
DAD
ALEW
ADAS
RRH
ALERW
RWALE
ADAH
ALEHZ
RW
RDDRV
ADRH
DAWH
PCLK
1
1
2
2
= (peripheral) clock period = 2 × t
2
PCLK
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set, else F = 0)
AD7–0 Data Setup Before RD High
AD7–0 Data Hold After RD High
AD15–8 Address to AD7–0 Data Valid
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
Delay Between RD Rising Edge to Next
Falling Edge
ALE Deasserted to Read Asserted
Read Deasserted to ALE Asserted
AD15–0 Address Hold After ALE Deasserted
ALE Deasserted to AD7–0 Address in High Z
RD Pulse Width
AD7–0 ALE Address Drive After Read High
AD15–8 Address Hold After RD High
AD15–8 Address to RD High
CCLK
DAD
or t
Rev. A | Page 26 of 52 | December 2006
DRS
as they are independent.
2 × t
Min
3.3
0
2 × t
t
H + t
F + H + 0.5
t
t
D – 2.0
F + H + t
H
D + t
PCLK
PCLK
PCLK
– 2.5
– 2.3
PCLK
PCLK
PCLK
PCLK
PCLK
– 2.0
– 3.8
– 1.4
– 4.0
PCLK
– 2.3
Max
D + t
t
PCLK
+ 3.0
PCLK
– 5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns