ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 5

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

SHARC FAMILY CORE ARCHITECTURE
The ADSP-2136x is code-compatible at the assembly level with
the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The
ADSP-2136x shares architectural features with the ADSP-2126x
and ADSP-2116x SIMD SHARC processors, as detailed in the
following sections.
SIMD Computational Engine
The ADSP-2136x contains two computational processing ele-
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive signal
processing algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
(OPTI ONA L)
(OPTI ONA L)
A DC
D AC
C LOC K
S D AT
S D AT
C LK
C LK
FS
FS
2
2
3
C LK IN
X TA L
C LK _C FG1-0
B OOTC FG1 -0
FLA G3-1
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
D AI _P 19
D A I_P 18
DA I_ P2 0
D A I_P1
DA I_ P2
DA I_ P3
DAI
R ES ET
ADSP-2136x
SR U
Figure 2. ADSP-2136x System Sample Configuration
C LK
FS
PC GA
P CG B
Rev. A | Page 5 of 52 | December 2006
SP OR T0-5
S C LK 0
S FS0
S D 0A
S D 0B
TIME R S
SPD IF
SR C
JTA G
ID P
S PI
6
CLK OU T
AD 1 5-0
FLA G0
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RD
bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the regis-
ter file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
elements. These computation units support IEEE 32-bit
single-precision floating-point, 40-bit extended-precision
floating-point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced
LA TCH
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