ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 32

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 28. Serial Ports—Enable and Three-State
1
Table 29. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
The t
This figure reflects changes made to support left-justified sample pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
1
1
1
1
1
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
Data Delay from Late External Transmit FS or External Receive
FS with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
NOTE: SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
DAI_P20 - 1
DAI_P20 - 1
(SCLK)
(SCLK)
(FS)
(FS)
DRIVE
DRIVE
t
DDTLFSE
Rev. A | Page 32 of 52 | December 2006
t
DDTLFSE
Figure 22. External Late Frame Sync
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
t
SFSE/I
SFSE/I
t
LATE EXTERNAL TRANSMIT FS
DDTENFS
t
DDTENFS
SAMPLE
SAMPLE
1ST BIT
DATA CHANNEL
1ST BIT
t
HDTE/I
t
HDTE/I
DRIVE
DRIVE
t
A/B) ARE ROUTED TO THE DAI_P20-1 PINS
HFSE/I
t
HFSE/I
Min
2
–1
Min
0.5
1
t
DDTE/I
t
DDTE/I
2ND BIT
2ND BIT
Max
7
Max
9
Unit
ns
ns
ns
Unit
ns
ns