ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 29

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-2136x is accessing external memory space.
Table 24. 8-Bit Memory Write Cycle
1
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
F = 7 × t
t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ALEW
ADAS
ALERW
RWALE
WRH
ADAH
WW
ADWL
ADWH
DWS
DWH
DAWH
PCLK
1
1
= (peripheral) clock period = 2 × t
PCLK
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × t
AD15 - 8
AD7 - 0
NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR
BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY
WRITES IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.
ALE
WR
RD
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to Next WR Falling Edge
AD15–0 Address Hold After ALE Deasserted
WR Pulse Width
AD15–8 Address to WR Low
AD15–8 Address Hold After WR High
AD7–0 Data Setup Before WR High
AD7–0 Data Hold After WR High
AD15–8 Address to WR High
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
CCLK
t
ALEW
t
ADAS
ADDRESS
ADDRESS
Figure 20. Write Cycle for 8-Bit Memory Timing
VALID
VALID
Rev. A | Page 29 of 52 | December 2006
t
t
ADAH
ADWL
t
ALERW
VALID ADDRESS
VALID DATA
t
t
DAWH
DWS
t
WW
t
WRH
VALID ADDRESS
PCLK
t
t
ADWH
DWH
VALID DATA
.
PCLK
.
Min
2 × t
t
2 × t
H + 0.5
F + H + t
t
D – F – 2.0
t
H
D – F + t
H
D – F + t
PCLK
PCLK
PCLK
t
RWALE
– 2.8
– 0.5
– 2.8
PCLK
PCLK
– 2.0
– 3.8
PCLK
PCLK
PCLK
– 4.0
– 4.0
– 2.3
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns