ADSP-21362WBBCZ-1A AD [Analog Devices], ADSP-21362WBBCZ-1A Datasheet - Page 2

• Manufacturer Part Number: ADSP-21362WBBCZ-1A
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
KEY FEATURES—PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-2136x
3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit
4M bit on-chip ROM (2M bit in block 0 and 2M bit in block 1)
Dual data address generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup, provid-
Single-instruction multiple-data (SIMD) architecture
Transfers between memory and core at a sustained
INPUT/OUTPUT FEATURES
DMA controller supports:
25 DMA channels for transfers between ADSP-2136x internal
32-bit DMA transfers at peripheral clock speed, in parallel
Asynchronous parallel port provides access to asynchronous
16 multiplexed address/data lines support 24-bit address
External memory access in a dedicated DMA channel
8-bit to 32-bit and 16-bit to 32-bit packing options
Programmable data cycle duration: 2 CCLK to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
Six dual data line serial ports that operate at up to 41.67M
Left-justified sample pair and I
TDM support for telecommunications interfaces including
performs 2 GFLOPS/666 MMACs
in blocks 2 and 3) for simultaneous access by the core pro-
cessor and DMA
reverse addressing
ing efficient program sequencing
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
Parallelism in buses and computational units allows single
5.4G bytes/s bandwidth at 333 MHz core instruction rate
memory and a variety of peripherals
with full-speed processor execution
external memory
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55M byte per sec transfer rate
cision clock generators, an input data port, three timers, an
S/PDIF transceiver, a DTCP cipher, an 8-channel asynchro-
nous sample rate converter, an SPI port, and a signal
routing unit
bits/s on each data line—each has a clock, frame sync, and
two data lines that can be configured as either a receiver or
transmitter pair
direction for up to 24 simultaneous receive or transmit
channels using two I
serial port
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
the assembly level
cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
2
S-compatible stereo devices per
2
S support, programmable
Rev. A | Page 2 of 52 | December 2006
Up to 12 TDM stream support, each with 128 channels per
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the pro-
Signal routing unit provides configurable and flexible con-
Two serial peripheral interfaces (SPI): primary on dedicated
3 muxed flag/IRQ lines
1 muxed flag/timer expired line
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter
Sample rate converter (SRC) contains a serial input port,
Pulse-width modulation provides:
ROM-based security features include:
PLL has a wide variety of software and hardware multi-
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA package (see
frame
cessor core, configurable as eight channels of serial data or
seven channels of serial data, and up to a 20-bit wide paral-
lel data channel
nections between all DAI components–six serial ports, one
SPI port, eight channels of asynchronous sample rate con-
verters, an S/PDIF receiver/transmitter, three timers, an SPI
port,10 interrupts, six flag inputs, six flag outputs, and
20 SRU I/O pins (DAI_Px)
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI
Full-duplex operation
Master slave mode multimaster support
Open drain outputs
Programmable baud rates, clock polarities, and phases
supports:
EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I
16-, 18-, 20- or 24-bit word widths (transmitter)
Two channel mode and single channel double frequency
(SCDF) mode
de-emphasis filter, sample rate converter (SRC) and serial
output port providing up to –140 dB SNR performance (see
Table 2 on Page
Supports left-justified, I
24-, 20-, 18-, and 16-bit serial formats (input)
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in nonpaired mode
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
plier/divider ratios
Page
access under program control to sensitive code
52)
2
S, or right-justified serial data input with
4)
2
S, TDM, and right-justified
Ordering Guide on