dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet
dsPIC33FJ32GP104-I/PT
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dsPIC33FJ32GP104-I/PT Summary of contents
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... PWM Support for: - Inverters, PFC, UPS - BLDC, PMSM, ACIM, SRM • Class B-Compliant Fault Inputs • Possibility of ADC Synchronization with PWM Signal 2011-2012 Microchip Technology Inc. dsPIC33FJ32(GP/MC)101/102/104 Advanced Analog Features • ADC module: - 10-bit, 1.1 Msps with four S&H ...
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... Y 13 PDIP, 4-ch SOIC 1 ADC SSOP 4-ch 1 ADC SPDIP, 6-ch SOIC, SSOP, QFN 1 ADC VTLA 6-ch 1 ADC PDIP, 4-ch SOIC, SSOP 1 ADC SPDIP, 6-ch SOIC, SSOP, QFN 1 ADC VTLA 6-ch 2011-2012 Microchip Technology Inc. ...
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... AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 2: dsPIC33FJ32(GP/MC)101/102/104 DEVICE FEATURES Device dsPIC33FJ32GP101 dsPIC33FJ32GP102 dsPIC33FJ32GP104 dsPIC33FJ32MC101 dsPIC33FJ32MC102 dsPIC33FJ32MC104 Note 1: Four out of five timers are remappable. ...
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... Pins are tolerant (1) RP15 /CN11/RB15 (1) RTCC/RP14 /CN12/RB14 V CAP V SS (1) SDA1/SDI1/RP9 /CN21/RB9 (1) SCL1/SDO1/RP8 /CN22/RB8 (1) SCK1/INT0/RP7 /CN23/RB7 (1) RP15 /CN11/RB15 (1) RTCC/RP14 /CN12/RB14 V CAP V SS (1) SDA1/RP9 /CN21/RB9 (1) SCL1/RP8 /CN22/RB8 (1) INT0/RP7 /CN23/RB7 2011-2012 Microchip Technology Inc. ...
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... PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV /C2INB/C1IND/RP1 REFIN REFOUT PGED3/SOSCI/RP4 PGEC3/SOSCO/T1CK/CN0/RA4 PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 PGED1/AN2/C2INA/C1INC/RP0 PGEC1/AN3/CV /CV REFIN REFOUT PGED3/SOSCI/AN9/RP4 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 Note 1: The RPn pins can be used by any remappable peripheral. See 2011-2012 Microchip Technology Inc. MCLR (1) /CN4/RB0 4 17 (1) /CN5/RB1 ...
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... RTCC/RP14 /CN12/RB14 25 (1) RP13 /CN13/RB13 24 (1) RP12 /CN14/RB12 23 (1) RP11 /CN15/RB11 22 (1) RP10 /CN16/RB10 CAP (1) SDA1/RP9 /CN21/RB9 18 (1) SCL1/RP8 /CN22/RB8 17 (1) INT0/RP7 /CN23/RB7 16 (1) 15 ASCL1/RP6 /CN24/RB6 for the list of available peripherals. 2011-2012 Microchip Technology Inc. ...
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... REFOUT PGED3/SOSCI/AN9/RP4 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 Note 1: The RPn pins can be used by any remappable peripheral. See 2: The PWM Fault pins are enabled and asserted during any Reset event. Refer to for more information on the PWM Faults. 2011-2012 Microchip Technology Inc. MCLR ...
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... (1) PWM1L1/RP15 /CN11/RB15 (1) PWM1H1/RTCC/RP14 /CN12/RB14 (1) PWM1L2/RP13 /CN13/RB13 (1) PWM1H2/RP12 /CN14/RB12 (1) PWM1L3/RP11 /CN15/RB11 (1) PWM1H3/RP10 /CN16/RB10 V CAP V SS (1) SDA1/RP9 /CN21/RB9 (1) SCL1/RP8 /CN22/RB8 (1) INT0/RP7 /CN23/RB7 (2) (1) FLTA1 /ASCL1/RP6 /CN24/RB6 for the list of available peripherals. Section 15.2 “PWM Faults” 2011-2012 Microchip Technology Inc. ...
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... REFOUT AN4/C3INC/C2INC/RP2 AN5/C3IND/C2IND/RP3 Note 1: The RPn pins can be used by any remappable peripheral. See 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc (1) /CN4/RB0 1 (1) /CN5/RB1 ...
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... OSCI/CLKI/CN30/RA2 6 OSCO/CLKO/CN29/RA3 Table 1 = Pins are tolerant 23 22 (1) RP13 /CN13/RB13 21 (1) RP12 /CN14/RB12 20 (1) RP11 /CN15/RB11 19 (1) RP10 /CN16/RB10 CAP (1) SDA1/RP9 /CN21/RB9 15 for the list of available peripherals. 2011-2012 Microchip Technology Inc. ...
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... The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally The PWM Fault pins are enabled and asserted during any Reset event. Refer to for more information on the PWM Faults. 2011-2012 Microchip Technology Inc ...
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... SS OSCI/CLKI/CN30/RA2 Table 1 = Pins are tolerant 22 (1) PWM1L2/RP13 /CN13/RB13 21 (1) PWM1H2/RP12 /CN14/RB12 20 (1) PWM1L3/RP11 /CN15/RB11 19 (1) PWM1H3/RP10 /CN16/RB10 CAP (1) SDA1/RP9 /CN21/RB9 15 for the list of available peripherals. Section 15.2 “PWM 2011-2012 Microchip Technology Inc. ...
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... AN5/C3IND/C2IND/RP3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGED3/SOSCI/RP4 Note 1: The RPn pins can be used by any remappable peripheral. See 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc (1) 1 /CN4/RB0 ...
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... Table 1 for the list of available peripherals. = Pins are tolerant ( RP13 /CN13/RB13 26 (1) RP12 /CN14/RB12 (1) 25 RP11 /CN15/RB11 (1) 24 RP10 /CN16/RB10 CAP N/C (1) SDA1/RP9 /CN21/RB9 2011-2012 Microchip Technology Inc. ...
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... The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally The PWM Fault pins are enabled and asserted during any Reset event. Refer to for more information on the PWM Faults. 2011-2012 Microchip Technology Inc ...
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... Table 1 for the list of available peripherals. = Pins are tolerant ( PWM1L2/RP13 /CN13/RB13 26 (1) PWM1H2/RP12 /CN14/RB12 25 (1) PWM1L3/RP11 /CN15/RB11 (1) 24 PWM1H3/RP10 /CN16/RB10 CAP N/C (1) 19 SDA1/RP9 /CN21/RB9 Section 15.2 “PWM Faults” 2011-2012 Microchip Technology Inc. ...
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... RP13 /CN13/RB13 Note 1: The RPn pins can be used by any remappable peripheral. See 2011-2012 Microchip Technology Inc dsPIC33FJ32GP104 Table 1 for the list of available peripherals. = Pins are tolerant (1) PEGED3/SOSCI/AN9/RP4 /CN1/RB4 ...
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... The PWM Fault pins are enabled and asserted during any Reset event. Refer to for more information on the PWM Faults. DS70652E-page dsPIC33FJ32MC104 Table 1 for the list of available peripherals. 2011-2012 Microchip Technology Inc. = Pins are tolerant (1) PEGED3/SOSCI/AN9/RP4 /CN1/RB4 RA8 OSC2/CLK0/CN29/RA3 OSC1/CLKI/CN30/RA2 (1) AN8/RP18 /CN10/RC2 (1) AN7/RP17 ...
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... The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc dsPIC33FJ32GP104 Table 1 = Pins are tolerant (1) ...
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... Table 1 = Pins are tolerant (1) PGED3/SOSCI/AN9/RP4 /CN1/RB4 RA8 OSC2/CLKO/CN29/RA3 OSC1/CLKI/CN30/RA2 (1) AN8/RP18 /CN10/RC2 (1) AN7/RP17 /CN9/RC1 (1) AN6/RP16 /CN8/RC0 (1) AN5/C3IND/C2IND/RP3 /CN7/RB3 (1) AN4/C3INC/C2INC/RP2 /CN6/RB2 for the list of available peripherals. Section 15.2 “PWM Faults” 2011-2012 Microchip Technology Inc. ...
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... The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS 2011-2012 Microchip Technology Inc PGED3/SOSCI/AN9/RP4 32 RA8 31 OSC2/CLKO/CN29/RA3 30 OSC1/CLKI/CN30/RA2 dsPIC33FJ32GP104 27 AN8/RP18 26 AN7/RP17 25 AN6/RP16 24 AN5/C3IND/C2IND/RP3 AN4/C3INC/C2INC/RP2 Table 1 for the list of available peripherals. = Pins are tolerant (1) /CN1/RB4 (1) ...
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... Table 1 = Pins are tolerant (1) PGED3/SOSCI/AN9/RP4 /CN1/RB4 RA8 OSC2/CLKO/CN29/RA3 OSC1/CLKI/CN30/RA2 (1) AN8/RP18 /CN10/RC2 (1) AN7/RP17 /CN9/RC1 (1) AN6/RP16 /CN8/RC0 (1) AN5/C3IND/C2IND/RP3 /CN7/RB3 (1) AN4/C3INC/C2INC/RP2 /CN6/RB2 for the list of available peripherals. Section 15.2 “PWM Faults” 2011-2012 Microchip Technology Inc. ...
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... Development Support............................................................................................................................................................... 275 26.0 Electrical Characteristics .......................................................................................................................................................... 279 27.0 Packaging Information.............................................................................................................................................................. 337 Appendix A: Revision History............................................................................................................................................................. 367 Index ................................................................................................................................................................................................. 375 The Microchip Web Site ..................................................................................................................................................................... 381 Customer Change Notification Service .............................................................................................................................................. 381 Customer Support .............................................................................................................................................................................. 381 Reader Response .............................................................................................................................................................................. 382 Product Identification System ............................................................................................................................................................ 383 2011-2012 Microchip Technology Inc. DS70652E-page 23 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70652E-page 24 to receive the most current information on all of our products. 2011-2012 Microchip Technology Inc. ...
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... Section 51. “Introduction (Part VI)” (DS70655) • Section 52. “Oscillator (Part VI)” (DS70644) • Section 53. “Interrupts (Part VI)” (DS70633) • Section 54. “Comparator with Blanking” (DS70647) • Section 55. “Charge Time Measurement Unit (CTMU)” (DS70635) 2011-2012 Microchip Technology Inc. product Web site 2 C™ ...
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... AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70652E-page 26 2011-2012 Microchip Technology Inc. ...
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... Family Reference Manual”, which are available from the Microchip web site (www.microchip.com). 2011-2012 Microchip Technology Inc. This data sheet contains device-specific information for dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ MC)101/102/104 Digital Signal Controller Devices. These devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture ...
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... ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-Bit ALU MCLR OC/ UART1 ADC1 PWM1-2 IC1-IC3 I2C1 CNx PORTA PORTB 16 Remappable Pins RTCC PWM 6-ch “Pin Diagrams” section for the specific pins 2011-2012 Microchip Technology Inc. ...
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... Not all pins are available on all devices. Refer to the specific device in the availability. 6: This pin is available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only. 2011-2012 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Data I/O pin for Programming/Debugging Communication Channel 3. Clock input pin for Programming/Debugging Communication Channel 3. Master Clear (Reset) input. This pin is an active-low Reset to the device. Analog = Analog input O = Output Section 15.2 “PWM Faults” Power I = Input for more “Pin Diagrams” section for 2011-2012 Microchip Technology Inc. ...
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... Not all pins are available on all devices. Refer to the specific device in the availability. 6: This pin is available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only. 2011-2012 Microchip Technology Inc. Description Positive supply for analog modules. This pin must be connected at all times connected the 18-pin dsPIC33FJXXGP101 and 20-pin ...
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... AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70652E-page 32 2011-2012 Microchip Technology Inc. ...
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... Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator 2011-2012 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS ...
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... V IH Section 26.0 additional Section 23.2 for details. provides two specific device and V ) and fast signal shown in Figure 2- Figure 2-2 within EXAMPLE OF MCLR PIN CONNECTIONS (1) (2) R1 MCLR dsPIC33F C and V specifications are met and V specifications are met. IL 2011-2012 Microchip Technology Inc. ...
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... REAL ICE™ In-Circuit Debugger User’s Guide” (DS51616) ® • “Using MPLAB REAL ICE™” (poster) (DS51749) 2011-2012 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “ ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternately, connect 10k resistor between V and unused pins. 2011-2012 Microchip Technology Inc. use certain result in all SS ...
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... As a result, three parameter instructions can be supported, allowing operations to be executed in a single cycle. 2011-2012 Microchip Technology Inc. A block diagram of the CPU is shown in the programmer’s model for the dsPIC33FJ16(GP/ MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 ...
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... Data Latch PCL X RAM Y RAM Address Address Loop Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support and 16-Bit ALU 16 To Peripheral Modules 2011-2012 Microchip Technology Inc. ...
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... TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 22 DOSTART OAB SAB DA SRH 2011-2012 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer ...
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... IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70652E-page 40 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/C-0 R-0 R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 2011-2012 Microchip Technology Inc. (2,3) DS70652E-page 41 ...
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... This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70652E-page 42 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) 2011-2012 Microchip Technology Inc. R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set ...
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... DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. 2011-2012 Microchip Technology Inc. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take and the same number of cycles to execute ...
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... AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70652E-page 44 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill 2011-2012 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 2011-2012 Microchip Technology Inc. 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • ...
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... Significant bit (LSb), bit 16 of the accumulator, of ACCxH is examined: • ‘1’, ACCxH is incremented. • ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. 2011-2012 Microchip Technology Inc. ...
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... For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. 2011-2012 Microchip Technology Inc. The MSb of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the ...
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... AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70652E-page 48 2011-2012 Microchip Technology Inc. ...
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... FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES Note 1: On Reset, these bits are automatically copied into the device Configuration Shadow registers. 2011-2012 Microchip Technology Inc. 4.1 Program Address Space The program address dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ MC)101/102/104 devices is 4M instructions ...
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... Alternate Vector Table 0x0001FE 0x000200 User Program Flash Memory (11.2K instructions) 0x0057FA 0x0057FC Flash Configuration (1) Words 0x0057FE 0x005800 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0xF7FFFE Device Configuration 0xF80000 Shadow Registers 0xF80020 0xF80022 Reserved 0xFEFFFE 0xFF0000 DEVID (2) 0xFFFFFE 2011-2012 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) 2011-2012 Microchip Technology Inc. 4.1.2 INTERRUPT AND TRAP VECTORS All dsPIC33FJ16(GP/MC)101/102 dsPIC33FJ32(GP/MC)101/102/104 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware ...
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... Additionally, the whole data space is addressable using MOV class of instructions, which support Memory Direct Addressing mode with a 16-bit address field using Indirect Addressing mode with a working register as an Address Pointer. These are used by the diagrams for device-specific 2011-2012 Microchip Technology Inc. ...
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... SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF 2011-2012 Microchip Technology Inc. LSB 16 Bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0x0BFE 0x0C00 ...
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... Optionally Mapped into Program Memory 0xFFFF DS70652E-page 54 LSB 16 Bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE 2011-2012 Microchip Technology Inc. 8 Kbyte Near Data Space ...
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... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class). 2011-2012 Microchip Technology Inc. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide two concurrent data read paths ...
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TABLE 4-1: CPU CORE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...
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TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 — — — CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 — — — CN12PUE CN11PUE ...
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TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF (2) IFS1 0086 ...
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TABLE 4-7: TIMERS REGISTER MAP FOR dsPIC33FJ16(GP/MC)10X DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E ...
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TABLE 4-9: INPUT CAPTURE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ...
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TABLE 4-12: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA ...
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TABLE 4-16: ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA ...
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TABLE 4-17: ADC1 REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA ...
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TABLE 4-18: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CTMUCON1 033A CTMUEN — CTMUSIDL TGEN CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> CTMUICON 033E ITRIM<5:0> Legend unknown value on Reset, — = unimplemented, ...
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TABLE 4-21: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0650 CMSIDL — — CVRCON 0652 — — — CM1CON 0654 CON COE CPOL CM1MSKSRC 0656 — — — CM1MSKCON 0658 HLMS — ...
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TABLE 4-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR2 06C4 — — — — RPOR3 06C6 — — — RPOR4 06C8 ...
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TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — ...
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TABLE 4-29: PORTA REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA 02C6 — ...
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TABLE 4-33: PORTB REGISTER MAP FOR dsPIC33FJ32GP101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 — — PORTB 02CA RB15 RB14 — — LATB 02CC LATB15 LATB14 — — ODCB 02CE ODCB15 ...
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TABLE 4-37: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> OSCTUN 0748 — — — — Legend ...
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... PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] 2011-2012 Microchip Technology Inc. 4.2.7 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM Segment for BS) is accessible only from the Boot Segment Flash code when enabled ...
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... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. 2011-2012 Microchip Technology Inc. ...
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... XMODSRT, XMODEND, YMODSRT, and YMODEND (see Table 4-1). Note: Y space Modulo Addressing EA calcula- tions assume word-sized data (LSb of every EA is always clear). 2011-2012 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by the difference corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...
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... W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value 2011-2012 Microchip Technology Inc. ...
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... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 2011-2012 Microchip Technology Inc. 4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • ...
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... A0 Decimal 2011-2012 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. 2011-2012 Microchip Technology Inc. 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is ...
Page 80
... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70652E-page 80 Program Counter 0 23 Bits 1/0 TBLPAG 8 Bits 24 Bits Select 1 0 PSVPAG 8 Bits 23 Bits 0 EA 1/0 16 Bits Bits Byte Select 2011-2012 Microchip Technology Inc. ...
Page 81
... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 2011-2012 Microchip Technology Inc. • TBLRDH (Table Read High Word mode, this instruction maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. ...
Page 82
... Any other iteration of the REPEAT loop will allow the instruction using PSV to access data, to execute in a single cycle. Data Space 0 0x000000 0x010000 0x018000 PSV Area 0x800000 2011-2012 Microchip Technology Inc. 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area ...
Page 83
... Using 1/0 Table Instruction User/Configuration Space Select 2011-2012 Microchip Technology Inc. ICSP allows a device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V Master Clear (MCLR) ...
Page 84
... To start a programming or erase sequence, the user application must consecutively write 0x55 and 47.4s = 0xAA to the NVMKEY register. Refer to “Programming Operations” Equation 5-3. 49.3s = Configuration Words, thereby (Register 5-1) controls which Section 5.3 for further details. 2011-2012 Microchip Technology Inc. ...
Page 85
... No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = No operation 0000 = No operation Note 1: These bits can only be reset on a POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 2011-2012 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 R/W-0 — Unimplemented bit, read as ‘0’ ...
Page 86
... Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) DS70652E-page 86 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
Page 87
... V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch 2011-2012 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of Reset will make the SYSRST sig- nal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state, and some are unaffected ...
Page 88
... If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70652E-page 88 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 89
... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 2011-2012 Microchip Technology Inc. (1) (CONTINUED) DS70652E-page 89 ...
Page 90
... Figure 6-2. Total Delay T OSCD (1) ( OSCD LOCK (1) ( OSCD OST (1) ( OSCD OST — (1) (2) ( OSCD OST LOCK (3) T LOCK (1) ( OSCD OST (1) T OSCD = 102.4 s for a OST 2011-2012 Microchip Technology Inc. ...
Page 91
... BOR Extension Time 100 s maximum T BOR T Power-up Time 64 ms nominal PWRT Delay 900 s maximum T Fail-Safe Clock FSCM Monitor Delay 2011-2012 Microchip Technology Inc. V BOR T BOR 3 T PWRT T OSCD Reset Time , ensures the voltage regulator output becomes stable. BOR for more information ...
Page 92
... BOR PWRT is too low (V < for proper DD DD BOR crosses the V threshold and the DD BOR , ensures BOR ) to ensure that the system PWRT for further + initiated each time V BOR PWRT trip point. BOR V BOR V BOR V BOR 2011-2012 Microchip Technology Inc. DD ...
Page 93
... Watchdog Reset. Refer to Section 23.4 “Watchdog Timer (WDT)” for more information on Watchdog Reset. 2011-2012 Microchip Technology Inc. 6.8 Trap Conflict Reset If a lower priority hard trap occurs while a higher priority trap is being processed, a hard Trap Conflict Reset occurs. The hard traps include exceptions of Priority Level 13 through Level 15, inclusive ...
Page 94
... MCLR Reset RESET instruction WDT Time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR — — 2011-2012 Microchip Technology Inc. ...
Page 95
... The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). 2011-2012 Microchip Technology Inc. Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority ...
Page 96
... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70652E-page 96 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) 2011-2012 Microchip Technology Inc. ...
Page 97
... Note 1: This interrupt vector is available in dsPIC33FJ(16/32)MC10X devices only. 2: This interrupt vector is available in dsPIC33FJ32(GP/MC)10X devices only. 3: This interrupt vector is available in dsPIC33FJ(16/32)MC102/104 devices only. 2011-2012 Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – ...
Page 98
... All Interrupt registers are described in through Register 7-28 Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved 7-1. For example, the INT0 (External Register 7-1 in the following pages. 2011-2012 Microchip Technology Inc. ...
Page 99
... IPL3: CPU Interrupt Priority Level Status bit CPU Interrupt Priority Level is greater than CPU Interrupt Priority Level less Note 1: For complete register details, see 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. 2011-2012 Microchip Technology Inc. (1) R/C-0 R-0 SB OAB (3) ...
Page 100
... Math error trap has occurred 0 = Math error trap has not occurred DS70652E-page 100 R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 OVBTE COVTE bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown ...
Page 101
... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. DS70652E-page 101 ...
Page 102
... INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS70652E-page 102 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...
Page 103
... IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — ...
Page 104
... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70652E-page 104 2011-2012 Microchip Technology Inc. ...
Page 105
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is available in dsPIC33FJ32(GP/MC)10X devices only. 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 U-0 (1) (1) T5IF T4IF — ...
Page 106
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown R/W-0 U-0 (1) PWM1IF — bit 8 ...
Page 107
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 FLTB1IF: PWM1 Fault B Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is available in dsPIC(16/32)MC102/104 devices only. 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
Page 108
... INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS70652E-page 108 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown ...
Page 109
... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: This bit is available in dsPIC33FJ32(GP/MC)10X devices only. 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 U-0 (1) (1) T5IE T4IE — ...
Page 110
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown R/W-0 U-0 (1) PWM1IE — bit 8 ...
Page 111
... U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is available in dsPIC(16/32)MC102/104 devices only. 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
Page 112
... Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70652E-page 112 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown ...
Page 113
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ...
Page 114
... Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70652E-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown ...
Page 115
... Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
Page 116
... Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70652E-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 CMIP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown ...
Page 117
... T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — U-0 U-0 R/W-1 — — ...
Page 118
... Interrupt source is disabled Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. DS70652E-page 118 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) T5IP<2:0> bit Bit is unknown ...
Page 119
... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC(16/32)MC10X devices only. 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 120
... Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC(16/32)MC10X devices only. DS70652E-page 120 R/W-0 U-0 R/W-1 (1) — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 RTCIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 121
... FLTB1IP<2:0>: PWM1 Fault B Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: These bits are available in dsPIC(16/32)MC102/104 devices only. 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 — ...
Page 122
... Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70652E-page 122 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 123
... Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is Number 135 • • • 0000001 = Interrupt Vector pending is Number 9 0000000 = Interrupt Vector pending is Number 8 2011-2012 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ...
Page 124
... Only user interrupts with a priority level lower can be disabled. Trap sources (Level 8-Level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of Priority Levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. 2011-2012 Microchip Technology Inc. ...
Page 125
... F are used interchangeably, except in the case of Doze mode used with a Doze ratio of 1:2 or lower. 2011-2012 Microchip Technology Inc. The oscillator system for dsPIC33FJ16(GP/MC)101/ 102 and dsPIC33FJ32(GP/MC)101/102/104 devices provides: • External and internal oscillator options as clock sources • ...
Page 126
... MHz are supported by the dsPIC33FJ16(GP/ MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 architecture. Instruction execution speed or device operating frequency given by: CY EQUATION 8-1: DEVICE OPERATING FREQUENCY F CY 2011-2012 Microchip Technology Inc. Configuration”. bits, FNOSC<2:0> bits, POSCMD<1:0> Table 8-1. is divided OSC ) and the CY ) ...
Page 127
... Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. 2011-2012 Microchip Technology Inc. EQUATION 8-2: MS WITH PLL MODE EXAMPLE 1 F OSC -- - 8000000 4 ...
Page 128
... PLL modes. DS70652E-page 128 (1) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Value set from Configuration bits on POR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) 2011-2012 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 129
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 2011-2012 Microchip Technology Inc. (1) (CONTINUED) ...
Page 130
... If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored. DS70652E-page 130 R/W-1 R/W-0 R/W-0 (2,3) (1,2,3) DOZEN U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) (1,2,3) R/W-0 R/W-0 FRCDIV<2:0> bit 8 U-0 U-0 U-0 — — — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 131
... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — ...
Page 132
... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. 2011-2012 Microchip Technology Inc. ...
Page 133
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode 2011-2012 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ MC)101/102/104 devices have two special power- saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 134
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). 2011-2012 Microchip Technology Inc. There are eight possible ® DSC ...
Page 135
... This bit is available in dsPIC33FJ32(GP/MC)10X devices only. 2: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — ...
Page 136
... OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70652E-page 136 (2) U-0 U-0 R/W-0 — — IC3MD U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown ...
Page 137
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ bit 2 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 1-0 Unimplemented: Read as ‘0’ 2011-2012 Microchip Technology Inc. U-0 U-0 R/W-0 — — CMPMD U-0 U-0 U-0 — — ...
Page 138
... AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70652E-page 138 2011-2012 Microchip Technology Inc. ...
Page 139
... Figure 10-1 how ports are shared with other peripherals and the associated I/O pin to which they are connected. 2011-2012 Microchip Technology Inc. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled ...
Page 140
... Peripheral Output Data PIO Module Read TRIS Data Bus D WR TRIS CK TRIS Latch D WR LAT + CK WR PORT Data Latch Read LAT Read PORT DS70652E-page 140 Output Multiplexers 1 Output Enable 0 1 Output Data I/O I/O Pin Input Data 2011-2012 Microchip Technology Inc. ...
Page 141
... PORTB<7:0> as outputs NOP ; Delay 1 cycle btss PORTB, #13 ; Next Instruction 2011-2012 Microchip Technology Inc. 10.3 Input Change Notification (ICN) The Input Change Notification function of the I/O ports allows the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 devices to gener- ate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins ...
Page 142
... RPx pin for input, the corresponding bit in the TRISx register must also be configured for input (i.e., set to ‘1’). FIGURE 10-2: REMAPPABLE MUX INPUT FOR U1RX U1RXR<4:0> 0 RP0 1 RP1 U1RX Input to Peripheral 2 RP2 2011-2012 Microchip Technology Inc. Register 10-1 a given ...
Page 143
... The list of peripherals for output mapping also includes a null value of ‘00000’ because of the mapping technique. This permits any given pin to remain unconnected from the output of any of the pin selectable peripherals. 2011-2012 Microchip Technology Inc. Function Name Register INT1 RPINR0 ...
Page 144
... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. 2011-2012 Microchip Technology Inc. (1) ...
Page 145
... This rule applies to all of the functions listed for a given pin. 2011-2012 Microchip Technology Inc. 4. Each CN pin has a configurable internal weak pull-up resistor. The pull-ups act as a current ...
Page 146
... Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ DS70652E-page 146 and R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS R/W-1 R/W-1 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 147
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits 11111 = Input tied to V 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 2011-2012 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 ...
Page 148
... Input tied to V 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70652E-page 148 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 149
... Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. 2011-2012 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS ...
Page 150
... Input tied to V 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70652E-page 150 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 151
... IC3R<4:0>: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits 11111 = Input tied to V 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 2011-2012 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 R/W-1 IC3R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 ...
Page 152
... Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70652E-page 152 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 153
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits 11111 = Input tied to V 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 2011-2012 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS ...
Page 154
... Input tied to RP1 00000 = Input tied to RP0 Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. DS70652E-page 154 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 (1) bit 8 R/W-1 R/W-1 (1) bit Bit is unknown (1) (1) 2011-2012 Microchip Technology Inc. ...
Page 155
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits 11111 = Input tied to V 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 2011-2012 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 ...
Page 156
... These bits are not available in dsPIC33FJXX(GP/MC)101 devices. DS70652E-page 156 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 (1) RP3R<4:0> R/W-0 R/W-0 R/W-0 (1) RP2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) (1) ...
Page 157
... Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: These bits are not available in dsPIC33FJ(16/32)(GP/MC)101 devices. 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R<4:0> ...
Page 158
... DS70652E-page 158 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 (1) RP11R<4:0> R/W-0 R/W-0 R/W-0 RP10R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 (1) bit Bit is unknown (1) (1) ...
Page 159
... Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-2 for peripheral function numbers) 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 160
... DS70652E-page 160 R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP19R<4:0> R/W-0 R/W-0 R/W-0 RP18R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 (1) bit 8 R/W-0 R/W-0 (1) bit Bit is unknown (1) (1) R/W-0 R/W-0 (1) bit 8 R/W-0 R/W-0 (1) bit Bit is unknown ...
Page 161
... Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only. 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP21R<4:0> R/W-0 R/W-0 R/W-0 RP20R<4:0> Unimplemented bit, read as ‘0’ ...
Page 162
... RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 10-2 for peripheral function numbers) Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only. DS70652E-page 162 R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 (1) bit 8 R/W-0 R/W-0 (1) bit Bit is unknown (1) (1) ...
Page 163
... TGATE 1 Set T1IF 0 Reset Equal 2011-2012 Microchip Technology Inc. Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal ...
Page 164
... When TCS = 1 and TON = 1, writes to the TMR1 register are inhibited from the CPU. DS70652E-page 164 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 (1) TCS — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 165
... T2CON, T3CON, T4CON and T5CON registers (see through Register 12-2). 2011-2012 Microchip Technology Inc. For 32-bit timer/counter operation, Timer2/4 is the least significant word (lsw) and Timer3/5 is the most significant word (msw) of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored ...
Page 166
... Where ‘x’ or ‘y’ are present DS70652E-page 166 1x Gate 01 Sync PRy PRx Comparator LSb TMRx TMRy TMRxHLD 16 (1,3,4) TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync To CTMU Filter 2011-2012 Microchip Technology Inc. ...
Page 167
... TIMER3 AND TIMER5 (16-BIT) BLOCK DIAGRAM Gate Sync Prescaler F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> To CTMU Filter Note 1: Timer5 is available in dsPIC33FJ32(GP/MC)10X devices only. 2011-2012 Microchip Technology Inc. 1x Gate Sync Sync TMRx Comparator PRx Falling Edge ...
Page 168
... External clock from pin, T2CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ DS70652E-page 168 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 169
... When 32-bit timer operation is enabled (T32 = 1) in the Timer2 Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer2 Control register (T2CON<3>), these bits have no effect. 2011-2012 Microchip Technology Inc. U-0 U-0 (1) — ...
Page 170
... Unimplemented: Read as ‘0’ Note 1: This register is available in dsPIC33FJ32(GP/MC)10X devices only. DS70652E-page 170 (1) U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 171
... When 32-bit timer operation is enabled (T32 = 1) in the Timer4 Control register (T4CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: When the 32-bit timer operation is enabled (T32 = 1) in the Timer4 Control register (T4CON<3>), these bits have no effect. 2011-2012 Microchip Technology Inc. (1) U-0 U-0 (2) — ...
Page 172
... AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70652E-page 172 2011-2012 Microchip Technology Inc. ...
Page 173
... ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. 2011-2012 Microchip Technology Inc. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1 ...
Page 174
... Input capture module turned off DS70652E-page 174 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown ...
Page 175
... TMR2 TMR3 2011-2012 Microchip Technology Inc. The output compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the Compare register value ...
Page 176
... Timer is Reset on Period Match (DS70209) for OCxR and OCx Interrupt Generation — OCx Rising Edge OCx Falling Edge OCx Rising and Falling Edge OCx Falling Edge OCx Falling Edge No Interrupt OCFA Falling Edge for OC1 to OC4 2011-2012 Microchip Technology Inc. ...
Page 177
... Initializes OCx pin low, generates single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initializes OCx pin high, compare event forces OCx pin low 001 = Initializes OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 178
... AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70652E-page 178 2011-2012 Microchip Technology Inc. ...
Page 179
... Fault pins to optionally drive each of the PWM output pins to a defined state • Duty cycle updates configurable to be immediate or synchronized to the PWM time base 2011-2012 Microchip Technology Inc. 15.1 PWM1: 6-Channel PWM Module This module simplifies the task of generating multiple synchronized PWM outputs ...
Page 180
... Override Logic PWM Channel 2 Dead-Time (1) Generator 2 Generator and Override Logic PWM (1) Channel 1 Dead-Time Generator 1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR PWM1H3 PWM1L3 PWM1H2 Output PWM1L2 Driver PWM1H1 Block PWM1L1 (2,3) FLTA1 (3) FLTB1 Special Event Trigger 2011-2012 Microchip Technology Inc. ...
Page 181
... Fault interrupt flag. After the Fault pin condition has been cleared, the PWM module restores the PWM output signals on the next PWM period or half-period boundary. 2011-2012 Microchip Technology Inc. Refer to Section 14. “Motor Control PWM” (DS70187), Reference Manual” for more information on the PWM Faults ...
Page 182
... Use builtin function to write 0x0000 to P1FLTBCON register __builtin_write_PWMSFR(&P1FLTBCON, 0x0000, &PWM1KEY); // Enable all PWMs using PWM1CON1 register // Writing to PWM1CON1 register requires unlock sequence // Use builtin function to write 0x0077 to PWM1CON1 register __builtin_write_PWMSFR(&PWM1CON1, 0x0077, &PWM1KEY); DS70652E-page 182 2011-2012 Microchip Technology Inc. ...
Page 183
... PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base operates in Single Pulse mode 00 = PWM time base operates in a Free-Running mode 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 184
... PTPER<14:0>: PWM Time Base Period Value bits DS70652E-page 184 R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PTPER<14:8> R/W-0 R/W-0 R/W-0 PTPER<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 185
... A Special Event Trigger will occur when the PWM time base is counting up bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits Note 1: SEVTDIR is compared with PTDIR (PxTMR<15>) to generate the Special Event Trigger. 2: PxSECMP<14:0> is compared with PxTMR<14:0> to generate the Special Event Trigger. 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 ...
Page 186
... If PWMPIN = 0, the PWM pins are controlled by the PWM module at Reset and are therefore, initially programmed as output pins. DS70652E-page 186 (1) U-0 U-0 R/W-0 — — PMOD3 R/W-0 U-0 R/W-0 (2) (2) PEN1H — PEN3L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) Section 15.3 “Write-Protected R/W-0 R/W-0 PMOD2 PMOD1 bit 8 R/W-0 R/W-0 (2) (2) (2) PEN2L PEN1L bit Bit is unknown 2011-2012 Microchip Technology Inc. ...
Page 187
... Output overrides via the PxOVDCON register occur on the next T bit 0 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled 2011-2012 Microchip Technology Inc. U-0 R/W-0 R/W-0 — ...
Page 188
... Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit A bits DS70652E-page 188 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 R/W-0 DTA<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 189
... DTS1A: Dead-Time Select for PWM1 Signal Going Active bit 1 = Dead time provided from Unit Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit Dead time provided from Unit A 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 190
... During any Reset event, FLTA1 is enabled by default and must be cleared as described in “PWM Faults”. DS70652E-page 190 (1,2,3,4) R/W-0 R/W-0 R/W-0 FAOV3L FAOV2H FAOV2L U-0 U-0 R/W-1 — — FAEN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Section 15.3 “Write-Protected Registers” 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 FAOV1H FAOV1L bit 8 R/W-1 R/W-1 FAEN2 FAEN1 bit Bit is unknown Section 15.2 ...
Page 191
... Refer to Table 15-1 for FLTB1 implementation details. 3: The PxFLTACON register is a write-protected register. Refer to for more information on the unlock sequence. 4: During any Reset event, FLTB1 is enabled by default and must be cleared as described in “PWM Faults”. 2011-2012 Microchip Technology Inc. (1,2,3,4) R/W-0 R/W-0 R/W-0 FBOV3L FBOV2H FBOV2L U-0 U-0 R/W-1 — ...
Page 192
... PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bits are cleared DS70652E-page 192 R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown ...
Page 193
... REGISTER 15-14: PxDC3: PWMx DUTY CYCLE REGISTER 3 R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PDC2<15:8> R/W-0 ...
Page 194
... PxFLTBCON registers are writable at all times. Refer to Section 14. “Motor Control PWM” (DS70187) in the “dsPIC33F/PIC24H Family Reference Manual” for details on the unlock sequence. DS70652E-page 194 R/W-0 R/W-0 R/W-0 PWMKEY<15:8> R/W-0 R/W-0 R/W-0 PWMKEY<7:0> Unimplemented, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 195
... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF 2011-2012 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift regis- ters, display drivers, Analog-to-Digital Converters, etc. ...
Page 196
... Section 18. “Serial Peripheral Interface (SPI)” (DS70206) in the “dsPIC33F/PIC24H Family Reference Manual”. • Code Samples • Application Notes • Software Libraries • Webinars • All related “dsPIC33F/PIC24H Family Reference Manual” sections • Development Tools 2011-2012 Microchip Technology Inc. ...
Page 197
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB. 2011-2012 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 198
... This bit must be cleared when FRMEN = not set both primary and secondary prescalers to a value of 1:1. DS70652E-page 198 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 (3) SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) 2011-2012 Microchip Technology Inc. R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 (3) PPRE<1:0> bit Bit is unknown ...
Page 199
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both primary and secondary prescalers to a value of 1:1. 2011-2012 Microchip Technology Inc. (3) (3) DS70652E-page 199 ...
Page 200
... Unimplemented: This bit must not be set to ‘1’ by the user application DS70652E-page 200 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011-2012 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 FRMDLY — bit Bit is unknown ...