dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 94

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
6.10.2
Any attempts to use the uninitialized W register as an
Address Pointer will reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.10.3
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a Security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine or other form of branch
instruction.
The VFC occurs when the Program Counter is
reloaded with an interrupt or trap vector.
TABLE 6-3:
DS70652E-page 94
TRAPR (RCON<15>)
IOPWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note: All Reset flag bits can be set or cleared by user software.
Flag Bit
UNINITIALIZED W REGISTER
RESET
SECURITY RESET
RESET FLAG BIT OPERATION
W register access or Security Reset
Illegal opcode or uninitialized
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
Configuration Mismatch
Trap conflict event
RESET instruction
WDT Time-out
MCLR Reset
POR, BOR
Set by:
POR
6.11
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Table 6-3
operation.
Note:
Using the RCON Status Bits
provides a summary of Reset flag bit
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
POR, BOR
POR, BOR
POR, BOR
POR
POR, BOR
PWRSAV instruction,
CLRWDT instruction, POR, BOR
POR, BOR
POR, BOR
 2011-2012 Microchip Technology Inc.
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