dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 237

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

REGISTER 20-4:
 2011-2012 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
R/W-0
HLMS
R/W-0
NAGS
bit 15
bit 7
HLMS: High or Low Level Masking Select bits
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
Unimplemented: Read as ‘0’
OCEN: OR Gate C Input Inverted Enable bit
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
OBEN: OR Gate B Input Inverted Enable bit
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
NAGS: Negative AND Gate Output Select
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
PAGS: Positive AND Gate Output Select
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
ACEN: AND Gate A1 C Input Inverted Enable bit
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
ACNEN: AND Gate A1 C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate
R/W-0
PAGS
U-0
—
CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
OCEN
R/W-0
ACEN
OCNEN
ACNEN
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
OBEN
R/W-0
ABEN
OBNEN
ABNEN
R/W-0
R/W-0
x = Bit is unknown
R/W-0
OAEN
R/W-0
AAEN
DS70652E-page 237
OANEN
AANEN
R/W-0
R/W-0
bit 8
bit 0