dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 133

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

9.0
The
dsPIC33FJ32(GP/MC)101/102/104 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. Devices can manage power
consumption in four different ways:
• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software-Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
9.1
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices allow a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by
simply changing the NOSCx bits (OSCCON<10:8>).
The process of changing a system clock during
operation, as well as limitations to the process, are
discussed in more detail in
Configuration”.
EXAMPLE 9-1:
 2011-2012 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note 1: This data sheet summarizes the features
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2: Some registers and associated bits
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
dsPIC33FJ16(GP/MC)101/102
of
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog
Timer
(DS70196) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
the
and
dsPIC33FJ16(GP/MC)101/102
PWRSAV INSTRUCTION SYNTAX
Power-Saving
; Put the device into SLEEP mode
; Put the device into IDLE mode
Section 8.0 “Oscillator
Modes”
and
in
9.2
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices have two special power-
saving modes that are entered through the execution of
a special PWRSAV instruction. Sleep mode stops clock
operation and halts all code execution. Idle mode halts
the CPU and code execution, but allows peripheral
modules to continue operation. The assembler syntax
of the PWRSAV instruction is shown in
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
9.2.1
The following occur in Sleep mode:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate,
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
• Any peripheral that requires the system clock
The device will wake-up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current
since the system clock source is disabled
the WDT is enabled
prior to entering Sleep mode
to operate. This includes items such as the Input
Change Notification (ICN) on the I/O ports, or
peripherals that use an external clock input.
source for its operation is disabled
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE
constants defined in the assembler
include file for the selected device.
and
IDLE_MODE
DS70652E-page 133
Example
9-1.
are